LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 649

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.8 MCPWM Capture read addresses
26.7.9 MCPWM Interrupt registers
7.9.1 MCPWM Interrupt Enable read address
The CAPCON register
MCI0-2 inputs as a capture event for each channel. When a channel’s capture event
occurs, the current TC value for that channel is stored in its read-only Capture register.
These addresses are read-only, but the underlying registers can be cleared by writing to
the CAP_CLR address
Table 560. MCPWM Capture read addresses (CAP - 0x400A 0044 (CAP0), 0x400A 0048
The Motor Control PWM module includes the following interrupt sources:
Table 561. Motor Control PWM interrupts
The INTEN register controls which of the MCPWM interrupts are enabled. This address is
read-only, but the underlying register can be modified by writing to addresses INTEN_SET
and INTEN_CLR.
Table 562. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description
Bit
31:0
Symbol
ILIM0/1/2
IMAT0/1/2
ICAP0/1/2
ABORT
Bit
0
1
2
3
4
Symbol
CAP
(CAP1), 0x400A 004C 9CAP2)) bit description
Symbol
ILIM0
IMAT0
ICAP0
-
ILIM1
All information provided in this document is subject to legal disclaimers.
Description
Limit interrupts for channels 0, 1, 2.
Match interrupts for channels 0, 1, 2.
Capture interrupts for channels 0, 1, 2.
Fast abort interrupt
Value
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Description
Current TC value at a capture event.
(Table
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
552) allows software to select any edge(s) on any of the
Description
Limit interrupt for channel 0.
Interrupt disabled.
Interrupt enabled.
Match interrupt for channel 0.
Interrupt disabled.
Interrupt enabled.
Capture interrupt for channel 0.
Interrupt disabled.
Interrupt enabled.
Reserved.
Limit interrupt for channel 1.
Interrupt disabled.
Interrupt enabled.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0000 00
00
0
0
0
Reset
value
0
-
649 of 1164