LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 342

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.22 Static Memory Write Enable Delay registers
Table 287. Static Memory Configuration registers (STATICCONFIG, address 0x4000 5200
[1]
[2]
The StaticWaitWen registers enable you to program the delay from the chip select to the
write enable. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 288. Static Memory Write Enable Delay registers (STATICWAITWEN, address
Bit
8
18:9
19
20
31:21 -
Bit
3:0
31:4
Extended wait and page mode cannot be selected simultaneously.
EMC may perform burst read access even when the buffer enable bit is cleared.
Symbol
EW
B
P
-
Symbol
WAITWEN
-
(STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240
(STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description
0x4000 5204 (STATICWAITWEN0), 0x4000 5224 (STATICWAITWEN1), 0x4000 5244
(STATICWAITWEN2), 0x4000 5264 (STATICWAITWEN3)) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
-
0
1
0
1
-
Wait write enable.
Description
Delay from chip select assertion to write enable.
0x0 = One CCLK cycle delay between assertion of chip select and
write enable (POR reset value).
0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x
tCCLK.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Extended wait.
Extended wait (EW) uses the StaticExtendedWait register to
time both the read and write transfers rather than the
StaticWaitRd and StaticWaitWr registers. This enables much
longer transactions.
Extended wait disabled (POR reset value).
Extended wait enabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Buffer enable
Buffer disabled (POR reset value).
Buffer enabled.
Write protect.
Writes not protected (POR reset value).
Write protected.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
[2]
.
[1]
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0
-
Reset
value
0
-
0
0
-