LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 417

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.5.1 Endpoint initialization
20.10.5 Managing endpoints
The USB 2.0 specification defines an endpoint, also called a device endpoint or an
address endpoint as a uniquely addressable portion of a USB device that can source or
sink data in a communications channel between the host and the device. The endpoint
address is specified by the combination of the endpoint number and the endpoint
direction.
The channel between the host and an endpoint at a specific device represents a data
pipe. Endpoint 0 for a device is always a control type data channel used for device
discovery and enumeration. Other types of endpoints support by USB include bulk,
interrupt, and isochronous. Each endpoint type has specific behavior related to packet
response and error handling. More detail on endpoint operation can be found in the USB
2.0 specification.
The LPC18xx supports up to six endpoints.
Each endpoint direction is essentially independent and can be configured with differing
behavior in each direction. For example, the DCD can configure endpoint 1-IN to be a bulk
endpoint and endpoint 1- OUT to be an isochronous endpoint. This helps to conserve the
total number of endpoints required for device operation. The only exception is that control
endpoints must use both directions on a single endpoint number to function as a control
endpoint. Endpoint 0 is, for example, is always a control endpoint and uses the pair of
directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum of 4
endpoint numbers, one for each endpoint direction are being used by the device
controller, then 8 queue heads are required. The operation of an endpoint and use of
queue heads are described later in this document.
After hardware reset, all endpoints except endpoint zero are un-initialized and disabled.
The DCD must configure and enable each endpoint by writing to configuration bit in the
ENDPTCTRLx register (see
and lower half. The lower half of ENDPTCTRLx is used to configure the receive or OUT
endpoint and the upper half is likewise used to configure the corresponding transmit or IN
endpoint. Control endpoints must be configured the same in both the upper and lower half
of the ENDPTCTRLx register otherwise the behavior is undefined. The following table
shows how to construct a configuration word for endpoint initialization.
Table 347. Device controller endpoint initialization
Field
Data Toggle Reset
Data Toggle Inhibit
Endpoint Type
Endpoint Stall
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
338). Each 32-bit ENDPTCTRLx is split into an upper
Value
1
0
00 - control
01 - isochronous
10 - bulk
11 - interrupt
0
UM10430
© NXP B.V. 2011. All rights reserved.
417 of 1164