LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1156

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
24.7.10
24.7.10.1 Configure the SCT . . . . . . . . . . . . . . . . . . . . 615
24.7.10.1.1 Configure the counter . . . . . . . . . . . . . . . . . 615
24.7.10.1.2 Configure the match and capture registers 615
24.7.10.1.3 Configure events and event responses . . . 616
Chapter 25: LPC18xx Timer0/1/2/3
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.7.1
25.7.2
25.7.3
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
26.1
26.2
26.3
26.4
26.5
26.5.1
26.6
26.7
26.7.1
26.7.1.1
26.7.1.2
26.7.1.3
26.7.2
26.7.2.1
26.7.2.2
26.7.2.3
26.7.3
26.7.4
26.7.5
26.7.5.1
26.7.5.2
26.7.5.3
26.7.6
26.7.7
Chapter 27: LPC18xx Quadrature Encoder Interface (QEI)
27.1
27.2
27.3
27.4
27.5
27.6
27.6.1
27.6.1.1
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 621
Basic configuration . . . . . . . . . . . . . . . . . . . . 621
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
General description . . . . . . . . . . . . . . . . . . . . 622
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 622
DMA connections. . . . . . . . . . . . . . . . . . . . . . 623
Register description . . . . . . . . . . . . . . . . . . . 623
How to read this chapter . . . . . . . . . . . . . . . . 635
Basic configuration . . . . . . . . . . . . . . . . . . . . 635
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
General description . . . . . . . . . . . . . . . . . . . . 635
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 637
Register description . . . . . . . . . . . . . . . . . . . 638
How to read this chapter . . . . . . . . . . . . . . . . 666
Basic configuration . . . . . . . . . . . . . . . . . . . . 666
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 669
Register description . . . . . . . . . . . . . . . . . . . 669
SCT operation . . . . . . . . . . . . . . . . . . . . . . . 615
Timer interrupt registers . . . . . . . . . . . . . . . . 624
Timer control registers . . . . . . . . . . . . . . . . . 625
Timer counter . . . . . . . . . . . . . . . . . registers 625
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 637
MCPWM Control register . . . . . . . . . . . . . . . 639
MCPWM Control read address . . . . . . . . . . 639
MCPWM Control set address . . . . . . . . . . . 641
MCPWM Control clear address . . . . . . . . . . 641
PWM Capture Control register . . . . . . . . . . . 642
MCPWM Capture Control read address . . . 642
MCPWM Capture Control set address . . . . 643
MCPWM Capture control clear address . . . 644
MCPWM Timer/Counter 0-2 registers . . . . . 646
MCPWM Limit 0-2 registers . . . . . . . . . . . . . 646
MCPWM Match 0-2 registers . . . . . . . . . . . . 647
Match register in Edge-Aligned mode. . . . . . 647
Match register in Center-Aligned mode . . . . 647
0 and 100% duty cycle . . . . . . . . . . . . . . . . . 647
MCPWM Dead-time register . . . . . . . . . . . . 647
MCPWM Communication Pattern register . . 648
Control registers . . . . . . . . . . . . . . . . . . . . . . 671
QEI Control register . . . . . . . . . . . . . . . . . . . 671
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
24.7.10.1.4 Configure multiple states . . . . . . . . . . . . . . 617
24.7.10.1.5 Miscellaneous options . . . . . . . . . . . . . . . 617
24.7.10.2 Operate the SCT . . . . . . . . . . . . . . . . . . . . . 617
24.7.10.3 Configure the SCT without using states. . . . 618
24.7.10.4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
25.7.4
25.7.5
25.7.6
25.7.7
25.7.8
25.7.9
25.7.10
25.7.11
25.7.12
25.8
25.9
26.7.8
26.7.9
7.9.1
26.7.9.2
26.7.9.3
26.7.9.4
26.7.9.5
26.7.9.6
26.7.10
26.7.10.1 MCPWM Count Control read address . . . . 655
26.7.10.2 MCPWM Count Control set address . . . . . . 656
26.7.10.3 MCPWM Count Control clear address . . . . 657
26.7.11
26.8
26.8.1
26.8.2
26.8.3
26.8.4
26.8.5
26.8.6
26.8.7
26.8.8
27.6.1.2
27.6.1.3
27.6.2
27.6.2.1
27.6.2.2
27.6.2.3
27.6.2.4
27.6.2.5
27.6.2.6
Example timer operation . . . . . . . . . . . . . . . 633
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Functional description . . . . . . . . . . . . . . . . . 660
Timer prescale registers . . . . . . . . . . . . . . . 625
Timer prescale counter registers . . . . . . . . . 626
Timer match control registers. . . . . . . . . . . . 626
Timer match registers (MR0 - MR3). . . . . . . 627
Timer capture control registers . . . . . . . . . . 628
Timer capture registers (CR0 - CR3) . . . . . . 629
Timer external match registers . . . . . . . . . . 629
Timer count control registers . . . . . . . . . . . . 631
DMA operation . . . . . . . . . . . . . . . . . . . . . . . 632
MCPWM Capture read addresses . . . . . . . 649
MCPWM Interrupt registers . . . . . . . . . . . . . 649
MCPWM Interrupt Enable read address . . . 649
MCPWM Interrupt Enable set address . . . . 650
MCPWM Interrupt Enable clear address . . 651
MCPWM Interrupt Flags read address . . . . 652
MCPWM Interrupt Flags set address . . . . . 653
MCPWM Interrupt Flags clear address . . . . 654
MCPWM Count Control register . . . . . . . . . 655
MCPWM Capture clear address . . . . . . . . . 659
Pulse-width modulation . . . . . . . . . . . . . . . . 660
Edge-aligned PWM without dead-time. . . . . . 660
Center-aligned PWM without dead-time . . . . 660
Dead-time counter . . . . . . . . . . . . . . . . . . . . . 661
Shadow registers and simultaneous updates 662
Fast Abort (ABORT). . . . . . . . . . . . . . . . . . . 662
Capture events. . . . . . . . . . . . . . . . . . . . . . . 662
External event counting (Counter mode) . . . 663
Three-phase DC mode . . . . . . . . . . . . . . . . 663
Three phase AC mode. . . . . . . . . . . . . . . . . 664
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
QEI Configuration register . . . . . . . . . . . . . 671
QEI Status register . . . . . . . . . . . . . . . . . . . 672
Position, index and timer registers. . . . . . . . 673
QEI Position register . . . . . . . . . . . . . . . . . . 673
QEI Maximum Position register . . . . . . . . . 673
QEI Position Compare register 0 . . . . . . . . 673
QEI Position Compare register 1 . . . . . . . . 673
QEI Position Compare register 2 . . . . . . . . 673
QEI Index Count register . . . . . . . . . . . . . . 674
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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