LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 498

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description
<Document ID>
User manual
Bit
25
26
27
29:28
31:30
Symbol
AAL
MB
TXPR
-
-
22.6.18 DMA Transmit poll demand register
Description
Address-aligned beats
When this bit is set high and the FB bit equals 1, the AHB interface generates all
bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst
(accessing the data buffer’s start address) is not aligned, but subsequent bursts are
aligned to the address.
Mixed burst
When this bit is set high and FB bit is low, the AHB master interface will start all bursts
of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst
transfers (INCRx and SINGLE) for burst-length of 16 and below.
When set, this bit indicates that the transmit DMA has higher priority than the
receive DMA during arbitration for the system-side bus.
Reserved
Table 422. Programmable burst length settings
The Transmit Poll Demand register enables the Transmit DMA to check whether or not the
current descriptor is owned by DMA. The Transmit Poll Demand command is given to
wake up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due
to an Underflow error in a transmitted frame or due to the unavailability of descriptors
owned by Transmit DMA. You can give this command anytime and the TxDMA will reset
this command once it starts re-fetching the current descriptor from host memory.
Table 423. DMA Transmit poll demand register (DMA_TRANS_POLL_DEMAND, address
Data bus width
32 bit
Bit
31:0
Symbol
TPD
0x4001 1004) bit description
All information provided in this document is subject to legal disclaimers.
Description
Transmit poll demand
When these bits are written with any value, the DMA reads
the current descriptor pointed to by the Current Host
Transmit Descriptor register
descriptor is not available (owned by Host), transmission
returns to the Suspend state and bit 2 in the DMA_STAT
Register is asserted. If the descriptor is available,
transmission resumes.
Rev. 00.13 — 20 July 2011
FIFO depth
128 bytes
256 bytes
512 bytes
1 kB
2 kB and above
(Section
22.6.27). If that
Chapter 22: LPC18xx Ethernet
Valid PBL range in full duplex
mode
8 or less
32 or less
64 or less
128 or less
all
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
Reset
value
0
498 of 1164
Access
R/W
R/W
R/W
RO
RO
Access
RO/WT