LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 117

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 91.
<Document ID>
User manual
Name
RESET_EXT_STAT46
RESET_EXT_STAT47
RESET_EXT_STAT48
RESET_EXT_STAT49
RESET_EXT_STAT50
RESET_EXT_STAT51
RESET_EXT_STAT52
RESET_EXT_STAT53
RESET_EXT_STAT54
RESET_EXT_STAT55
RESET_EXT_STAT56
RESET_EXT_STAT57
RESET_EXT_STAT58
RESET_EXT_STAT59
RESET_EXT_STAT60
RESET_EXT_STAT61
RESET_EXT_STAT62
RESET_EXT_STAT63
Register overview: RGU (base address: 0x4005 3000)
11.4.1 RGU reset control register
The RGU reset control register allows software to activate and clear individual reset
outputs. Each bit corresponds to an individual reset output, and writing a one activates
that output. The reset output is automatically de-activated after a fixed delay period. If the
reset output has a manual release, it stays activated once pulled low until a 0 is written to
the appropriate bit in this register. This applies whether the reset activation came from the
Reset Control Register or any other source
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
Address
offset
0x4B8
0x4BC
0x4C0
0x4C4
0x4C8
0x4CC
0x4D0
0x4D4
0x4D8
0x4DC
0x4E0
0x4E4
0x4E8
0x4EC
0x4F0
0x4F4
0x4F8
0x4FC
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reset external status register 46 for
UART2_RST
Reset external status register 47 for
UART3_RST
Reset external status register 48 for
I2C0_RST
Reset external status register 49 for
I2C1_RST
Reset external status register 50 for
SSP0_RST
Reset external status register 51 for
SSP1_RST
Reset external status register 52 for
I2S_RST
Reset external status register 53 for
SPIFI_RST
Reset external status register 54 for
CAN1_RST
Reset external status register 55 for
CAN0_RST
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Chapter 11: LPC18xx Reset Generation Unit (RGU)
…continued
Reset value Reference
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
UM10430
© NXP B.V. 2011. All rights reserved.
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Table 105
Table 105
Table 105
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Table 105
Table 105
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Table 105
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