LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 275

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.6.17 DMA Channel Destination Address registers
16.6.18 DMA Channel Linked List Item registers
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the address may have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 211. DMA Channel Source Address Registers (CSRCADDR, 0x4000 2100
The eight read/write CDESTADDR Registers (C0DESTADDR to C7DESTADDR) contain
the current destination address (byte-aligned) of the data to be transferred. Each register
is programmed directly by software before the channel is enabled. When the DMA
channel is enabled the register is updated as the destination address is incremented and
by following the linked list when a complete packet of data has been transferred. Reading
the register when the channel is active does not provide useful information. This is
because by the time that software has processed the value read, the address may have
progressed. It is intended to be read only when a channel has stopped, in which case it
shows the destination address of the last item read.
Table 212. DMA Channel Destination Address registers (CDESTADDR, 0x4000 2104
The eight read/write CLLI Registers (C0LLI to C7LLI) contain a word-aligned address of
the next Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain,
and the DMA channel is disabled when all DMA transfers associated with it are
completed. Programming this register when the DMA channel is enabled may have
unpredictable side effects.
Bit
31:0
Bit
31:0
•
•
As the source address is incremented.
By following the linked list when a complete packet of data has been transferred.
Symbol
SRCADDR
(C0SRCADDR) to 0x4000 21E0 (C7SRCADDR)) bit description
(C0DESTADDR) to 0x4000 21E4 (C7DESTADDR)) bit description
Symbol
DESTADDR
All information provided in this document is subject to legal disclaimers.
Description
DMA source address. Reading this register will
return the current source address.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
DMA Destination address. Reading this
register will return the current destination
address.
Reset value
0x0000 0000 R/W
Reset value
0x0000 0000 R/W
UM10430
© NXP B.V. 2011. All rights reserved.
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