LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 722

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0),
Bit Symbol
2
3
4
5
6
PE
FE
BI
THRE
TEMT
0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Parity Error.
When the parity bit of a received character is in the wrong state, a
parity error occurs. A LSR read clears LSR[2]. Time of parity error
detection is dependent on FCR[0].
Note: A parity error is associated with the character at the top of
the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
Framing Error.
When the stop bit of a received character is a logic 0, a framing
error occurs. A LSR read clears LSR[3]. The time of the framing
error detection is dependent on FCR0. Upon detection of a
framing error, the RX will attempt to re-synchronize to the data
and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will be
correct even if there is no Framing Error.
Note: A framing error is associated with the character at the top
of the UART RBR FIFO.
Framing error status is inactive.
Framing error status is active.
Break Interrupt.
When RXD1 is held in the spacing state (all zeros) for one full
character transmission (start, data, parity, stop), a break interrupt
occurs. Once the break condition has been detected, the receiver
goes idle until RXD1 goes to marking state (all ones). A LSR read
clears this status bit. The time of break detection is dependent on
FCR[0].
Note: The break interrupt is associated with the character at the
top of the UART RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
Transmitter Holding Register Empty.
THRE is set immediately upon detection of an empty UART THR
and is cleared on a THR write.
THR contains valid data.
THR is empty.
Transmitter Empty.
TEMT is set when both THR and TSR are empty; TEMT is
cleared when either the TSR or the THR contain valid data.
THR and/or the TSR contains valid data.
THR and the TSR are empty.
Chapter 32: LPC18xx USART0_2_3
UM10430
…continued
© NXP B.V. 2011. All rights reserved.
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Reset
Value
0
0
0
1
1