LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 294

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

17.1 How to read this chapter
17.2 Basic configuration
17.3 Features
17.4 General description
<Document ID>
User manual
The SPIFI is available on all LPC18xx parts.
The SPIFI is configured as follows:
Table 219. SPIFI clocking and power control
The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected to
the Cortex-M3 processor with little performance penalty compared to parallel flash
devices with higher pin count.
A driver API included in on-chip ROM handles setup, programming and erasure. After an
initialize call to the SPIFI driver, the flash content is accessible as normal memory using
byte, halfword, and word accesses by the processor and/or DMA channels.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization. Quad devices then use a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices, and includes extensions to help insure compatibility with
future devices.
Serial flash devices respond to commands sent by software or automatically sent by the
SPIFI when software reads either of the two read-only serial flash regions in the memory
map (see
SPIFI AHB register clock (HCLK) BASE_M3_CLK
SPIFI serial clock input (SCKI)
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UM10430
Chapter 17: LPC18xx SPI Flash Interface (SPIFI)
Rev. 00.13 — 20 July 2011
See
The SPIFI is reset by the SPIFI_RST (reset # 53).
Interfaces to serial flash memory in the main memory map.
Supports 1-, 2-, and 4-bit bidirectional serial protocols.
Half-duplex protocol compatible with various vendors and devices.
Data rates of up to 66 MB per second.
Table 219
Table
All information provided in this document is subject to legal disclaimers.
220).
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_SPIFI_CLK
Branch clock
CLK_M3_SPIFI
SPIFI_CLK
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
132 MHz
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