LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 66

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

9.1 How to read this chapter
9.2 Basic configuration
9.3 Features
9.4 General description
<Document ID>
User manual
Remark: This chapter describes the clock generation of parts LPC1850/30/20/10 Rev ‘A’
and parts LPC18xx (with on-chip flash). Note that register clocks and clock control
registers are specific to parts LPC1850/30/20/10 rev “A” and parts LPC18xx (with on-chip
flash). For a description of the CGU of parts LPC1850/30/20/10 Rev ‘-’, see
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See
Section
The CGU is configured as follows:
Table 43.
The CGU generates multiple independent clocks for the core and the peripheral blocks of
the LPC18x. Each independent clock is called a base clock and itself is one of the inputs
to the two Clock Control Units (CCUs) which control the branch clocks to the individual
peripherals (see
CGU
•
•
•
•
•
•
UM10430
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Rev. 00.13 — 20 July 2011
See
Do not reset the CGU during normal operation.
PLL control
Oscillator control
Clock generation and clock source multiplexing
Five integer dividers
1.3. The corresponding clock control registers are reserved.
Table 43
CGU clocking and power control
Base clock
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
Chapter
for clocking and power control.
Rev. 00.13 — 20 July 2011
10).
Branch clock
CLK_M3_BUS
Maximum frequency
150 MHz
© NXP B.V. 2011. All rights reserved.
User manual
Section
66 of 1164
42.4.