LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 838

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.7.2.1 Software initialization
36.7.2.2 CAN message transfer
36.7.2 C_CAN operating modes
The software initialization is started by setting the bit INIT in the CAN Control Register,
either by software or by a hardware reset, or by entering the busoff state.
During software initialization (INIT bit is set), the following conditions are present:
To initialize the CAN controller, software has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to
not valid. Otherwise, the whole message object has to be initialized.
Resetting the INIT bit finishes the software initialization. Afterwards the Bit Stream
Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the
occurrence of a sequence of 11 consecutive recessive bits (Bus Idle) before it can take
part in bus activities and starts the message transfer.
Remark: The initialization of the Message Objects is independent of INIT and also can be
done on the fly, but the Message Objects should all be configured to particular identifiers
or set to not valid during software initialization before the BSP starts the message transfer.
To change the configuration of a Message Object during normal operation, the CPU has to
start by setting the MSGVAL bit to not valid. When the configuration is completed,
MSAGVALis set to valid again.
Once the CAN controller is initialized and INIT is reset to zero, the CAN core synchronizes
itself to the CAN bus and starts the message transfer.
Received messages are stored into their appropriate Message Objects if they pass the
Message Handler’s acceptance filtering. The whole message including all arbitration bits,
DLC and eight data bytes is stored into the Message Object. If the Identifier Mask is used,
the arbitration bits which are masked to “don’t care” may be overwritten in the Message
Object.
The CPU may read or write each message any time via the Interface Registers. The
Message Handler guarantees data consistency in case of concurrent accesses.
Messages to be transmitted are updated by the CPU. If a permanent Message Object
(arbitration and control bits set up during configuration) exists for the message, only the
data bytes are updated and then TXRQUT bit with NEWDAT bit are set to start the
transmission. If several transmit messages are assigned to the same Message Object
(when the number of Message Objects is not sufficient), the whole Message Object has to
be configured before the transmission of this message is requested.
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All message transfer from and to the CAN bus is stopped.
The status of the CAN output CAN_TXD is recessive (HIGH).
The EML counters are unchanged.
The configuration registers are unchanged.
Access to the bit timing register and the BRP extension register is enabled if the CCE
bit in the CAN control register is also set.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
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