LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 276

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL))
<Document ID>
User manual
Bit
11:0
bit description
Symbol
TRANSFERSIZE
16.6.19 DMA channel control registers
Table 213. DMA Channel Linked List Item registers (CLLI, 0x4000 2108 (C0LLI) to 0x4000
The eight read/write CCONTROL Registers (C0CONTROL to C7CONTROL) contain
DMA channel control information such as the transfer size, burst size, and transfer width.
Each register is programmed directly by software before the DMA channel is enabled.
When the channel is enabled the register is updated by following the linked list when a
complete packet of data has been transferred. Reading the register while the channel is
active does not give useful information. This is because by the time software has
processed the value read, the channel may have advanced. It is intended to be read only
when a channel has stopped.
Bit
0
1
31:2
Value Description
Symbol
LM
R
LLI
21E8 (C7LLI)) bit description
Transfer size in number of transfers. A write to this field sets the
size of the transfer when the DMA Controller is the flow
controller. The transfer size value must be set before the
channel is enabled. Transfer size is updated as data transfers
are completed.
A read from this field indicates the number of transfers
completed on the destination bus. Reading the register when
the channel is active does not give useful information because
by the time that the software has processed the value read, the
channel might have progressed. It is intended to be used only
when a channel is enabled and then disabled.
The transfer size value is not used if the DMA Controller is not
the flow controller.
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
AHB master select for loading the next LLI:
AHB Master 0.
AHB Master 1.
Reserved, and must be written as 0, masked on
read.
Linked list item. Bits [31:2] of the address for the
next LLI. Address bits [1:0] are 0.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0
Reset
value
0
0
0x0000
0000
276 of 1164
Access
R/W
Access
R/W
R/W
R/W