LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 496

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description
<Document ID>
User manual
Bit
0
1
6:2
7
Symbol
SWR
DA
DSL
ATDS
22.6.17 DMA Bus mode register
Description
Software reset
When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal
registers and logic. It is cleared automatically after the reset operation has completed
in all of the core clock domains. Read a 0 value in this bit before re-programming any
register of the core.
Remark: The reset operation is completed only when all the resets in all the active
clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks
(applicable for the selected PHY interface) are present for software reset completion.
DMA arbitration scheme
0 = Round-robin with Rx:Tx priority given in bits [15:14]
1 = Rx has priority over Tx
Descriptor skip length
This bit specifies the number of Word/Dword/Lword (depending on 32/64/128-bit bus)
to skip between two unchained descriptors. The address skipping starts from the end
of current descriptor to the start of next descriptor. When DSL value equals zero, then
the descriptor table is taken as contiguous by the DMA, in Ring mode.
Alternate (Enhanced) descriptor size
When set, the alternate (enhanced) descriptor (see
32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or
Full IPC Offload Engine is enabled in the receiver.
When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).
This bit is present only when Alternate Descriptor feature is selected and either
Advanced Time Stamp or IPC Full Checksum Offload (type 2) feature is selected
during configuration. Otherwise, this bit is reserved and read-only.
Table 420. Time stamp snapshot dependency on register bits
The Bus Mode register establishes the bus operating modes for the DMA.
TSCLKTYPE TSMSTRENA TSEVNTENA
10
11
11
N/A
N/A
N/A
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
1
0
1
Section
Messages for which snapshot is taken
SYNC, Follow_Up
SYNC, Follow_Up, Delay_Req, Delay_Resp,
Pdelay_Req, Pdelay_Resp
SYNC, Pdelay_Req, Pdelay_Resp
22.9) size is increased to
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
496 of 1164
Access
R/WS/
SC
R/W
R/W
R/W