LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1127

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 248. Transferred CIU Card Byte Count Register
Table 249. Transferred Host to BIU-FIFO Byte Count
Table 250. Debounce Count Register (DEBNCE, address
Table 251. User ID Register (USRID, address 0x4000 4068)
Table 252. Version ID Register (VERID, address 0x4000
Table 253. UHS-1 Register (UHS_REG, address 0x4000
Table 254. Hardware Reset (RST_N, address 0x4000 4078)
Table 255. Bus Mode Register (BMOD, address 0x4000
Table 256. Poll Demand Register (PLDMND, address
Table 257. Descriptor List Base Address Register
Table 258. Internal DMAC Status Register (IDSTS, address
Table 259. Internal DMAC Interrupt Enable Register
Table 260. Current Host Descriptor Address Register
Table 261. Current Buffer Descriptor Address Register
Table 262. EMC clocking and power control . . . . . . . . . .322
Table 263. Memory bank selection . . . . . . . . . . . . . . . . .324
Table 264. EMC pin description . . . . . . . . . . . . . . . . . . .325
Table 265. Register overview: External memory controller
Table 266. EMC Control register (CONTROL - address
Table 267. EMC Status register (STATUS - address
Table 268. EMC Configuration register (CONFIG - address
Table 269. Dynamic Control register (DYNAMICCONTROL -
Table 270. Dynamic Memory Refresh Timer register
Table 271. Dynamic Memory Read Configuration register
Table 272. Dynamic Memory Precharge Command Period
Table 273. Dynamic Memory Active to Precharge Command
<Document ID>
User manual
(TCBCNT, address 0x4000 405C) bit description.
315
Register (TBBCNT, address 0x4000 4060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .316
0x4000 4064) bit description . . . . . . . . . . . . .316
bit description . . . . . . . . . . . . . . . . . . . . . . . . .316
406C) bit description. . . . . . . . . . . . . . . . . . . .316
4074) bit description . . . . . . . . . . . . . . . . . . . .317
bit description . . . . . . . . . . . . . . . . . . . . . . . . .317
4080) bit description . . . . . . . . . . . . . . . . . . . .317
0x4000 4084) bit description . . . . . . . . . . . . .318
(DBADDR, address 0x4000 4088) bit description
318
0x4000 408C) bit description . . . . . . . . . . . . .319
(IDINTEN, address 0x4000 4090) bit description .
320
(DSCADDR, address 0x4000 4094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .320
(BUFADDR, address 0x4000 4098) bit description
321
(base address 0x4000 5000) . . . . . . . . . . . . .325
0x4000 5000) bit description . . . . . . . . . . . . .328
0x4000 5008) bit description . . . . . . . . . . . . .328
0x4000 5008) bit description . . . . . . . . . . . . .329
address 0x4000 5020) bit description. . . . . . .329
(DYNAMICREFRESH - address 0x4000 5024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .331
(DYNAMICREADCONFIG - address
0x4000 5028) bit description . . . . . . . . . . . . .332
register (DYNAMICRP - address 0x4000 5030) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Period register (DYNAMICRAS - address
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 274. Dynamic Memory Self Refresh Exit Time register
Table 275. Dynamic Memory Last Data Out to Active Time
Table 276. Dynamic Memory Data In to Active Command
Table 277. Dynamic Memory Write Recovery Time register
Table 278. Dynamic Memory Active to Active Command
Table 279. Dynamic Memory Auto Refresh Period register
Table 280. Dynamic Memory Exit Self Refresh register
Table 281. Dynamic Memory Active Bank A to Active Bank B
Table 282. Dynamic Memory Load Mode register to Active
Table 283. Static Memory Extended Wait register
Table 284. Dynamic Memory Configuration registers
Table 285. Address mapping . . . . . . . . . . . . . . . . . . . . . 338
Table 286. Dynamic Memory RASCAS Delay registers
Table 287. Static Memory Configuration registers
Table 288. Static Memory Write Enable Delay registers
Table 289. Static Memory Output Enable delay registers
0x4000 5034) bit description . . . . . . . . . . . . . 333
(DYNAMICSREX - address 0x4000 5038) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
register (DYNAMICAPR - address 0x4000 503C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 333
Time register (DYNAMICDAL - address
0x4000 5040) bit description . . . . . . . . . . . . . 334
(DYNAMICWR - address 0x4000 5044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Period register (DYNAMICRC - address
0x4000 5048) bit description . . . . . . . . . . . . . 335
(DYNAMICRFC - address 0x4000 504C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
(DYNAMICXSR - address 0x4000 5050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Time register (DYNAMICRRD - address
0x4000 5054) bit description . . . . . . . . . . . . . 336
Command Time (DYNAMICMRD - address
0x4000 5058) bit description . . . . . . . . . . . . . 336
(STATICEXTENDEDWAIT - address
0x4000 5080) bit description . . . . . . . . . . . . . 337
(DYNAMICCONFIG, address 0x4000 5100
(DYNAMICCONFIG0), 0x4000 5120
(DYNAMICCONFIG1), 0x4000 5140
(DYNAMICCONFIG2), 0x4000 5160
(DYNAMICCONFIG3)) bit description . . . . . . 337
(DYNAMICRASCAS, address 0x4000 5104
(DYNAMICRASCAS0), 0x4000 5124
(DYNAMICRASCAS1), 0x4000 5144
(DYNAMICRASCAS2), 0x4000 5164
(DYNAMICRASCAS3)) bit description. . . . . . 340
(STATICCONFIG, address 0x4000 5200
(STATICCONFIG0), 0x4000 5220
(STATICCONFIG1), 0x4000 5240
(STATICCONFIG2), 0x4000 5260
(STATICCONFIG3)) bit description . . . . . . . . 341
(STATICWAITWEN, address 0x4000 5204
(STATICWAITWEN0), 0x4000 5224
(STATICWAITWEN1), 0x4000 5244
(STATICWAITWEN2), 0x4000 5264
(STATICWAITWEN3)) bit description. . . . . . . 342
(STATICWAITOEN, address 0x4000 5208
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
1127 of 1164