LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1157

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
27.6.2.7
27.6.2.8
27.6.2.9
27.6.2.10 QEI Velocity register . . . . . . . . . . . . . . . . . . 674
27.6.2.11 QEI Velocity Capture register . . . . . . . . . . . 675
27.6.2.12 QEI Velocity Compare register . . . . . . . . . . 675
27.6.2.13 QEI Digital filter on phase A input register . . 675
27.6.2.14 QEI Digital filter on phase B input register . . 675
27.6.2.15 QEI Digital filter on index input register . . . . 675
27.6.2.16 QEI Index acceptance window register . . . . 676
27.6.2.17 QEI Index Compare register 1 . . . . . . . . . . . 676
27.6.2.18 QEI Index Compare register 2 . . . . . . . . . . . 676
27.6.3
27.6.3.1
Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT)
28.1
28.2
28.3
28.4
28.5
Chapter 29: LPC18xx Alarm timer
29.1
29.2
29.3
29.4
29.4.1
29.4.2
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
30.1
30.2
30.3
30.4
30.5
30.5.1
30.6
30.7
Chapter 31: LPC18xx Real-Time Clock (RTC)
31.1
31.2
31.3
31.4
31.5
31.6
31.6.1
31.6.2
31.6.3
31.6.4
31.6.5
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 684
Basic configuration . . . . . . . . . . . . . . . . . . . . 684
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
General description . . . . . . . . . . . . . . . . . . . . 684
Register description . . . . . . . . . . . . . . . . . . . 685
How to read this chapter . . . . . . . . . . . . . . . . 688
Basic configuration . . . . . . . . . . . . . . . . . . . . 688
General description . . . . . . . . . . . . . . . . . . . . 688
Register description . . . . . . . . . . . . . . . . . . . 689
How to read this chapter . . . . . . . . . . . . . . . . 691
Basic configuration . . . . . . . . . . . . . . . . . . . . 691
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Register description . . . . . . . . . . . . . . . . . . . 693
How to read this chapter . . . . . . . . . . . . . . . . 699
Basic configuration . . . . . . . . . . . . . . . . . . . . 699
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
General description . . . . . . . . . . . . . . . . . . . . 699
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 700
Register description . . . . . . . . . . . . . . . . . . . 701
QEI Index Compare register 0 . . . . . . . . . . . 674
QEI Timer Reload register . . . . . . . . . . . . . . 674
QEI Timer register . . . . . . . . . . . . . . . . . . . . 674
Interrupt registers . . . . . . . . . . . . . . . . . . . . . 677
QEI Interrupt Enable Clear register . . . . . . . 677
Downcounter register . . . . . . . . . . . . . . . . . . 689
Preset value register. . . . . . . . . . . . . . . . . . . 689
WWDT behavior in debug mode. . . . . . . . . . 692
Interrupt Location Register . . . . . . . . . . . . . 702
Clock Control Register . . . . . . . . . . . . . . . . . 702
Counter Increment Interrupt Register . . . . . 703
Alarm Mask Register . . . . . . . . . . . . . . . . . . 703
Consolidated time registers . . . . . . . . . . . . . 704
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
27.6.3.2
27.6.3.3
27.6.3.4
27.6.3.5
27.6.3.6
27.7
27.7.1
27.7.1.1
27.7.1.2
27.7.2
27.7.3
27.7.4
28.5.1
28.5.2
28.5.3
28.5.4
28.6
29.4.3
29.4.4
29.4.5
29.4.6
29.4.7
29.4.8
30.7.1
30.7.2
30.7.3
30.7.4
30.7.5
30.7.6
30.8
30.9
31.6.5.1
31.6.5.2
31.6.5.3
31.6.6
31.6.6.1
31.6.6.2
31.6.7
31.7
31.7.1
Functional description . . . . . . . . . . . . . . . . . 680
RI timer operation . . . . . . . . . . . . . . . . . . . . . 686
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 697
Watchdog timing examples . . . . . . . . . . . . . 697
Functional description . . . . . . . . . . . . . . . . . 710
QEI Interrupt Enable Set register . . . . . . . . 677
QEI Interrupt Status register . . . . . . . . . . . . 678
QEI Interrupt Enable register . . . . . . . . . . . 679
QEI Interrupt Clear register . . . . . . . . . . . . . 679
QEI Interrupt Set register . . . . . . . . . . . . . . 680
Input signals. . . . . . . . . . . . . . . . . . . . . . . . . 681
Quadrature input signals . . . . . . . . . . . . . . . 681
Digital input filtering . . . . . . . . . . . . . . . . . . . 682
Position capture . . . . . . . . . . . . . . . . . . . . . . 682
Velocity capture . . . . . . . . . . . . . . . . . . . . . . 682
Velocity compare . . . . . . . . . . . . . . . . . . . . . 683
RI Compare Value register . . . . . . . . . . . . . 685
RI Mask register . . . . . . . . . . . . . . . . . . . . . 685
RI Control register . . . . . . . . . . . . . . . . . . . . 685
RI Counter register . . . . . . . . . . . . . . . . . . . 686
Interrupt clear enable register . . . . . . . . . . . 689
Interrupt set enable register . . . . . . . . . . . . . 690
Interrupt status register . . . . . . . . . . . . . . . . 690
Interrupt enable register. . . . . . . . . . . . . . . . 690
Clear status register. . . . . . . . . . . . . . . . . . . 690
Set status register . . . . . . . . . . . . . . . . . . . . 690
Watchdog mode register . . . . . . . . . . . . . . . 693
Watchdog timer constant register . . . . . . . . 695
Watchdog feed register . . . . . . . . . . . . . . . . 695
Watchdog timer value register . . . . . . . . . . 696
Watchdog timer warning interrupt register . 696
Watchdog timer window register . . . . . . . . . 696
Consolidated Time Register 0 . . . . . . . . . . . 704
Consolidated Time Register 1 . . . . . . . . . . . 704
Consolidated Time Register 2 . . . . . . . . . . . 705
Time Counter Group . . . . . . . . . . . . . . . . . . 705
Leap year calculation . . . . . . . . . . . . . . . . . . 707
Calibration register . . . . . . . . . . . . . . . . . . . 707
Alarm register group . . . . . . . . . . . . . . . . . . 708
Calibration procedure. . . . . . . . . . . . . . . . . . 710
Backward calibration . . . . . . . . . . . . . . . . . . . 710
Forward calibration . . . . . . . . . . . . . . . . . . . . 710
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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