LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 222

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 133. GIMA inputs
Each GIMA output control consists of five stages:
If the source generates shorter pulses than the output clock, the source pulses can be
missed. In this case, the asynchronous capture stage can be used to capture the rising
edge, the synchronizer stage synchronizes the edge to the peripheral clock and pulse
generator stage can optionally generate a singe cycle pulse. (By default the generated
pulse is two clock cycles.)
Remark: Use the capture and the synchronizer stage together to avoid the creation of
very short, spurious pulses.
Input
53
54
55
56
57
58
59
60
61
62
63
1. Input selection
2. Input inversion: inverts the path between source and destination.
3. Asynchronous capture
4. Synchronization to peripheral clock
5. Pulse generation
Source
pin T3_CAP2
pin T3_CAP3
T0 MAT0
T0 MAT2
T0 MAT3
T1 MAT2
T1 MAT3
T2 MAT0
T2 MAT3
T3 MAT2
T3 MAT3
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Possible connections to peripheral blocks
T3 CAP2
T3 CAP3
VADC
Event router
channel 13
T1 CAP3
Event router
channel 14
T2 CAP3
VADC
T3 CAP3
Event router
channel 16
T0 CAP3
ADC start0
conversion
(ADC CR
register bit
START = 0x2)
ADC start1
conversion
(ADC CR
register bit
START = 0x3)
UM10430
© NXP B.V. 2011. All rights reserved.
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