LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 335

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.14 Dynamic Memory Auto-refresh Period register
19.7.15 Dynamic Memory Exit Self Refresh register
Table 278. Dynamic Memory Active to Active Command Period register (DYNAMICRC -
The DynamicTRFC register enables you to program the auto-refresh period, and
auto-refresh to active command period, tRFC. It is recommended that this register is
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. This value is normally found in SDRAM data sheets as
tRFC, or sometimes as tRC. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 279. Dynamic Memory Auto Refresh Period register (DYNAMICRFC - address
The DynamicTXSR register enables you to program the exit self-refresh to active
command time, tXSR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tXSR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 280. Dynamic Memory Exit Self Refresh register (DYNAMICXSR - address
Bit
4:0
31:5
Bit
4:0
31:5
Bit
4:0
31:5
Symbol
tRC
Symbol
tRFC
-
-
Symbol
tXSR
-
address 0x4000 5048) bit description
0x4000 504C) bit description
0x4000 5050) bit description
All information provided in this document is subject to legal disclaimers.
Description
Active to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Auto-refresh period and auto-refresh to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Exit self-refresh to active command time.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
335 of 1164
Reset
value
0x1F
-
Reset
value
0x1F
-
Reset
value
0x1F
-