LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 181

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 107. Pin description
<Document ID>
User manual
Symbol
DBGEN
TCK/SWDCLK
TRST
TMS/SWDIO
TDO/SWO
TDI
USB0 pins
USB0_DP
USB0_DM
USB0_VBUS
USB0_ID
USB0_RREF
USB1 pins
USB1_DP
USB1_DM
I
I2C0_SCL
I2C0_SDA
Reset and wake-up pins
RESET
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
ADC pins
ADC0_0/
ADC1_0/DAC
2
C-bus pins
L4
J5
M4
K6
K5
J4
F2
G2
F1
H2
H1
F12
G12
L15
L16
D9
A9
A10
C9
D8
E3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
…continued
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
-
-
-
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
-
-
-
x
28
27
29
30
31
26
18
20
21
22
24
89
90
92
93
128
130
-
-
-
6
All information provided in this document is subject to legal disclaimers.
[3]
[3]
[3]
[3]
[3]
[3]
[7]
[7]
[7]
[8]
[8]
[9]
[9]
[10]
[10]
[11]
[11]
[11]
[11]
[11]
[8]
Rev. 00.13 — 20 July 2011
Reset
state
[2]
I; PD
I; F
I; PU
I; PU
O; PU
I; PU
-
-
-
-
-
-
-
I; F
I; F
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I
I
I
I
I
I
I
I
I
I
Type Description
I
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
JTAG interface control signal. Also used for boundary
Test Clock for JTAG interface (default) or Serial Wire
Test Mode Select for JTAG interface (default) or SW
Test Data In for JTAG interface.
External reset input: A LOW on this pin resets the device,
External wake-up input; can raise an interrupt and can
External wake-up input; can raise an interrupt and can
External wake-up input; can raise an interrupt and can
External wake-up input; can raise an interrupt and can
ADC input channel 0. Shared between 10-bit ADC0/1 and
scan.
(SW) clock.
Test Reset for JTAG interface.
debug data input/output.
Test Data Out for JTAG interface (default) or SW trace
output.
USB0 bidirectional D+ line.
USB0 bidirectional D line.
VBUS pin (power on USB cable).
Indicates to the transceiver whether connected to an
A-device (LOW) or a B-device (HIGH).
12.0 k (accuracy 1%) on-board resistor to ground for
current reference.
USB1 bidirectional D+ line.
USB1 bidirectional D line.
I
compliance).
I
compliance).
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
cause wake-up from any of the low power modes.
cause wake-up from any of the low power modes.
cause wake-up from any of the low power modes.
cause wake-up from any of the low power modes.
DAC.
2
2
C clock input/output. Open-drain output (for I
C data input/output. Open-drain output (for I
Chapter 12: LPC18xx Pin configuration
UM10430
© NXP B.V. 2011. All rights reserved.
2
2
C-bus
C-bus
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