LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 394

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 336. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description
Table 337. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description
<Document ID>
User manual
Bit
5:0
15:6
21:16 ETCE
31:21 -
Bit
0
1
3:2
6:4
7
15:8
Symbol
RXS
-
RXT1_0
-
RXE
-
Symbol
ERCE
-
20.6.23 USB Endpoint 0 Control register (ENDPTCTRL0)
Value
0
1
-
-
-
Description
Endpoint receive complete event for physical OUT endpoints 5 to 0.
This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred.
ERCE0 = endpoint 0
...
ERCE5 = endpoint 5
reserved
Endpoint transmit complete event for physical IN endpoints 5 to 0.
This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT)
occurred.
ETCE0 = endpoint 0
...
ETCE5 = endpoint 5
reserved
Writing a one will clear the corresponding bit in this register.
This register initializes endpoint 0 for control transfer. Endpoint 0 is always a control
endpoint.
Description
Rx endpoint stall
Endpoint ok.
Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.
reserved
Endpoint type
Endpoint 0 is always a control endpoint.
reserved
Rx endpoint enable
Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
[1]
Reset
value
0
-
0
-
Reset
value
0
00
-
1
-
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/WC
-
R/WC
-
R/W
R/W
-
Access
RO
-
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