LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 691

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

30.1 How to read this chapter
30.2 Basic configuration
30.3 Features
<Document ID>
User manual
The WWDT is identical for all LPC18xx parts.
The WWDT is configured as follows:
Table 621. WWDT clocking and power control
Clock to WWDT register interface
(PCLK)
Watchdog clock (WDCLK)
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UM10430
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
Rev. 00.13 — 20 July 2011
See
clock (WDCLK) is the IRC.
The WWDT cannot be reset by software.
The WWDT interrupt is connected to slot # 7 in the Event router.
Internally resets chip if not reloaded during the programmable time-out period.
Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Programmable 24 bit timer with internal fixed pre-scaler.
Selectable time period from 1,024 watchdog clocks (T
million watchdog clocks (T
Safe watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
Incorrect feed sequence causes immediate watchdog reset if enabled.
The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
Flag to indicate Watchdog reset.
The WWDT uses the IRC as a fixed clock source.
Table 621
All information provided in this document is subject to legal disclaimers.
for clocking and power control. The only clock source for the WWDT
Rev. 00.13 — 20 July 2011
WDCLK
Base clock
BASE_M3_CLK
BASE_SAFE_CLK
 2
24
 4) in increments of 4 watchdog clocks.
Branch clock
CLK_M3_WWDT 150 MHz
-
WDCLK
 256  4) to over 67
Maximum
frequency
12 MHz (fixed
frequency)
© NXP B.V. 2011. All rights reserved.
User manual
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