LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 517

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.1.3 Buffer size calculations
22.8.1.4 DMA arbiter for MAC-DMA and MAC-AHB cores
Example: Buffer read
If the Transmit buffer address is 0x00000FF2 (for 32-bit data bus), and 15 bytes need to
be transferred, then the DMA reads five full words from address 0x00000FF0, but when
transferring data to the MTL Transmit FIFO, the extra bytes (the first two bytes) are
dropped or ignored. Similarly, the last 3 bytes of the last transfer are also ignored. The
DMA always ensures it transfers a full 32-bit data to the MTL Transmit FIFO, unless it is
the end-of-frame.
Example: Buffer write
If the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a
received frame need to be transferred, then the DMA writes 3 full words from address
0x00000FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transfer
have dummy data.
The DMA does not update the size fields in the Transmit and Receive descriptors. The
DMA updates only the status fields (RDES and TDES) of the descriptors. The driver has
to perform the size calculations.
The transmit DMA transfers the exact number of bytes (indicated by buffer size field of
TDES1) towards the MAC core. If a descriptor is marked as first (FS bit of TDES1 is set),
then the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is
marked as last (LS bit of TDES1), then the DMA marks the last transfer from that data
buffer as the end-of frame to the MTL.
The Receive DMA transfers data to a buffer until the buffer is full or the end-of frame is
received from the MTL. If a descriptor is not marked as last (LS bit of RDES0), then the
descriptor’s corresponding buffer(s) are full and the amount of valid data in a buffer is
accurately indicated by its buffer size field minus the data buffer pointer offset when the
FS bit of that descriptor is set. The offset is zero when the data buffer pointer is aligned to
the data bus width. If a descriptor is marked as last, then the buffer may not be full (as
indicated by the buffer size in RDES1). To compute the amount of valid data in this final
buffer, the driver must read the frame length (FL bits of RDES0[29:16]) and subtract the
sum of the buffer sizes of the preceding buffers in this frame. The Receive DMA always
transfers the start of next frame with a new descriptor.
Remark: Even when the start address of a receive buffer is not aligned to the system
bus’s data width, the system should allocate a receive buffer of a size aligned to the
system bus width. For example, if the system allocates a 1,024-byte (1 KB) receive buffer
starting from address 0x1000, the software can program the buffer start address in the
Receive descriptor to have a 0x1002 offset. The Receive DMA writes the frame to this
buffer with dummy data in the first two locations (0x1000 and 0x1001). The actual frame is
written from location 0x1002. Thus, the actual useful space in this buffer is 1,022 bytes,
even though the buffer size is programmed as 1,024 bytes, because of the start address
offset.
The arbiter inside the DMA module performs the arbitration between the Transmit and
Receive channel accesses to the AHB Master interface. Two types of arbitrations are
possible: round-robin, and fixed-priority.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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