LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 515

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 46. Descriptor ring and chain structure
22.8.1 Initialization
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor n
Ring Structure
addressed, rather than contiguous buffers in memory.
A data buffer resides in the Host physical memory space, and consists of an entire frame
or part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer
status is maintained in the descriptor. Data chaining refers to frames that span multiple
data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to
the next frame buffer when end-of-frame is detected. Data chaining can be enabled or
disabled.
Follow these steps to initialize the ethernet controller:
1. Write to DMA Register
2. Write to DMA Register
3. The software driver creates the Transmit and Receive descriptor lists. Then it writes to
4. Write to MAC Registers
both DMA Register
the starting address of each list.
options.
All information provided in this document is subject to legal disclaimers.
Buffer 1
Buffer 2
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Buffer 2
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Rev. 00.13 — 20 July 2011
Table 425
Table 421
Table 429
Table
and DMA Register
404,
to set Host bus access parameters.
to mask unnecessary interrupt causes.
Table
406, and
Next Descriptor
Descriptor 0
Descriptor 1
Descriptor 2
Table
Table 405
Chain Structure
Chapter 22: LPC18xx Ethernet
426, providing the DMA with
for desired filtering
UM10430
© NXP B.V. 2011. All rights reserved.
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