LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 853

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

37.1 How to read this chapter
37.2 Basic configuration
37.3 Features
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User manual
The I2C-bus interfaces I2C0 and I2C1 are available on all LPC18xx parts.
The I2C0/1 are configured as follows:
Table 798. I2C0/1 clocking and power control
Clock to the I2C0 register interface and
I2C0 peripheral clock.
Clock to the I2C1 register interface and
I2C1 peripheral clock.
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UM10430
Chapter 37: LPC18xx I2C-bus interface
Rev. 00.13 — 20 July 2011
See
The I2C0/1 are reset by the I2C0/1_RST (reset # 48/49).
The I2C0/1 interrupts are connected to slots # 18/19 in the NVIC.
Configure the I2C0 pins for Fast-mode Plus, Fast mode, or Standard mode through
the SFSI2C0 register in the SYSCON block (see
Standard I
Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
Programmable clock allows adjustment of I
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
Supports Fast-mode Plus.
Optional recognition of up to four distinct slave addresses.
Monitor mode allows observing all I
I
The I
2
C-bus can be used for test and diagnostic purposes.
Table 798
2
C-bus contains a standard I
2
C-compliant bus interfaces may be configured as Master, Slave, or
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_APB1_CLK
BASE_APB3_CLK
2
C-compliant bus interface with two pins.
2
C-bus traffic, regardless of slave address.
2
C transfer rates.
Table
Branch clock
CLK_APB1_I2C0
CLK_APB3_I2C1
205).
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
150 MHz
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