LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 317

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 255. Bus Mode Register (BMOD, address 0x4000 4080) bit description
<Document ID>
User manual
Bit
0
1
6:2
7
Symbol
SWR
FB
DSL
DE
18.6.29 UHS-1 Register (UHS_REG)
18.6.30 Hardware Reset (RST_N)
18.6.31 Bus Mode Register (BMOD)
Value
Table 253. UHS-1 Register (UHS_REG, address 0x4000 4074) bit description
Table 254. Hardware Reset (RST_N, address 0x4000 4078) bit description
Bit
15:0
31:16 DDR_REG
Bit
15:0
31:16
Description
Software Reset. When set, the DMA Controller resets all its internal registers. SWR
is read/write. It is automatically cleared after 1 clock cycle.
Fixed Burst. Controls whether the AHB Master interface performs fixed burst
transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or
INCR16 during start of normal burst transfers. When reset, the AHB will use
SINGLE and INCR burst transfer operations. FB is read/write.
Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending
on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable
only for dual buffer structure. DSL is read/write.
IDMAC Enable. When set, the IDMAC is enabled. DE is read/write.
Symbol
VOLT_REG High Voltage mode. Determines the voltage fed to the buffers by an
Symbol
CARD_RESET
-
All information provided in this document is subject to legal disclaimers.
Description
external voltage regulator.
0 - Buffers supplied with 3.3V Vdd
1 - Buffers supplied with 1.8V Vdd
These bits function as the output of the host controller and are fed
to an external voltage regulator. The voltage regulator must switch
the voltage of the buffers of a particular card to either 3.3V or 1.8V,
depending on the value programmed in the register. VOLT_REG[0]
should be set to 1 for card number 0 in order to make it operate for
1.8V.
DDR mode. Determines the voltage fed to the buffers by an
external voltage regulator.
0 - Non-DDR mode
1 - DDR mode
UHS_REG [16] should be set for card number 0, UHS_REG [17] for
card number 1 and so on.
Rev. 00.13 — 20 July 2011
Description
Hardware reset.
1 - Active mode
0 - Reset
These bits cause the cards to enter pre-idle state, which
requires them to be re-initialized. CARD_RESET[0]
should be set to 1 to reset card number 0, and
CARD_RESET[15] should be set to reset card number
15. The number of bits implemented is restricted to
NUM_CARDS.
Reserved
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
317 of 1164
Reset
value
0
0
Reset
value
0
0
0