LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 703

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
31.6.3 Counter Increment Interrupt Register
31.6.4 Alarm Mask Register
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
1 to bit 0 of the Interrupt Location Register (ILR[0]).
Table 636. Counter Increment Interrupt Register (CIIR - address 0x4004 600C) bit description
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 637
alarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the counter
comparison first changes from no match to match. The interrupt is removed when a one is
written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are
set, then the alarm is disabled.
Table 637. Alarm Mask Register (AMR - address 0x4004 6010) bit description
Bit
0
1
2
3
4
5
6
7
31:8
Bit
0
1
2
3
4
5
6
7
31:8
Symbol
IMSEC
IMMIN
IMHOUR
IMDOM
IMDOW
IMDOY
IMMON
IMYEAR
-
Symbol
AMRSEC
AMRMIN
AMRHOUR When 1, the Hour value is not compared for the alarm.
AMRDOM
AMRDOW
AMRDOY
AMRMON
AMRYEAR When 1, the Year value is not compared for the alarm.
-
shows the relationship between the bits in the AMR and the alarms. For the
All information provided in this document is subject to legal disclaimers.
Description
When 1, an increment of the Second value generates an interrupt.
When 1, an increment of the Minute value generates an interrupt.
When 1, an increment of the Hour value generates an interrupt.
When 1, an increment of the Day of Month value generates an
interrupt.
When 1, an increment of the Day of Week value generates an
interrupt.
When 1, an increment of the Day of Year value generates an interrupt. 0
When 1, an increment of the Month value generates an interrupt.
When 1, an increment of the Year value generates an interrupt.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
When 1, the Second value is not compared for the alarm.
When 1, the Minutes value is not compared for the alarm.
When 1, the Day of Month value is not compared for the alarm.
When 1, the Day of Week value is not compared for the alarm.
When 1, the Day of Year value is not compared for the alarm.
When 1, the Month value is not compared for the alarm.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 31: LPC18xx Real-Time Clock (RTC)
UM10430
© NXP B.V. 2011. All rights reserved.
703 of 1164
Reset
value
0
0
0
0
0
0
0
0
NA
Reset
value
0
0
0
0
0
0
0
NA