LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1125

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 152. SCT CTIN_1 capture input multiplexer
Table 153. SCT CTIN_2 capture input multiplexer
Table 154. SCT CTIN_3 capture input multiplexer
Table 155. SCT CTIN_4 capture input multiplexer
Table 156. SCT CTIN_5 capture input multiplexer
Table 157. SCT CTIN_6 capture input multiplexer
Table 158. SCT CTIN_7 capture input multiplexer
Table 159. ADC trigger input multiplexer
Table 160. Event router input 13 multiplexer
Table 161. Event router input 14 multiplexer
Table 162. Event router input 16multiplexer
Table 163. ADC start0 input multiplexer (ADCSTART0_IN,
Table 164. ADC start1 input multiplexer (ADCSTART1_IN,
Table 165. GPIO pins available . . . . . . . . . . . . . . . . . . . .245
Table 166. GPIO clocking and power control . . . . . . . . .245
Table 167. Register overview: GPIO pin interrupts (base
Table 168. Register overview: GPIO GROUP0 interrupt
Table 169. Register overview: GPIO GROUP1 interrupt
Table 170. Register overview: GPIO port (base address
Table 171. Pin interrupt mode register (ISEL, address
Table 172. Pin interrupt level (rising edge interrupt enable)
Table 173. Pin interrupt level (rising edge interrupt) set
Table 174. Pin interrupt level (rising edge interrupt) clear
<Document ID>
User manual
(CTIN_1_IN, address 0x400C 7044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .237
(CTIN_2_IN, address 0x400C 7048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .237
(CTIN_3_IN, address 0x400C 704C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .238
(CTIN_4_IN, address 0x400C 7050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .238
(CTIN_5_IN, address 0x400C 7054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .239
(CTIN_6_IN, address 0x400C 7058) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(CTIN_7_IN, address 0x400C 705C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(VADC_TRIGGER_IN, address 0x400C 7060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
(EVENTROUTER_13_IN, address 0x400C 7064)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .241
(EVENTROUTER_14_IN, address 0x400C 7068)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .242
(EVENTROUTER_16_IN, address 0x400C 706C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .243
address 0x400C 7070) bit description . . . . . .243
address 0x400C 7074) bit description . . . . . .244
address: 0x4008 7000) . . . . . . . . . . . . . . . . . .248
(base address 0x4008 8000) . . . . . . . . . . . . .248
(base address 0x4008 9000) . . . . . . . . . . . . .249
0x400F 4000) . . . . . . . . . . . . . . . . . . . . . . . . .250
0x4008 7000) bit description . . . . . . . . . . . . .252
register (IENR, address 0x4008 7004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .252
register (SIENR, address 0x4008 7008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .253
register (PCIENR, address 0x4008 700C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .253
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 175. Pin interrupt active level (falling edge interrupt
Table 176. Pin interrupt active level (falling edge interrupt)
Table 177. Pin interrupt active level (falling edge interrupt)
Table 178. Pin interrupt rising edge register (RISE, address
Table 179. Pin interrupt falling edge register (FALL, address
Table 180. Pin interrupt status register (IST address 0x4008
Table 181. GPIO grouped interrupt control register (CTRL,
Table 182. GPIO grouped interrupt port polarity registers
Table 183. GPIO grouped interrupt port n enable registers
Table 184. GPIO port byte pin registers (B, addresses
Table 185. GPIO port word pin registers (W, addresses
Table 186. GPIO port direction register (DIR, addresses
Table 187. GPIO port mask register (MASK, addresses
Table 188. GPIO port pin register (PIN, addresses 0x400F
Table 189. GPIO masked port pin register (MPIN, addresses
Table 190. GPIO port set register (SET, addresses 0x400F
Table 191. GPIO port clear register (CLR, addresses 0x400F
Table 192. GPIO port toggle register (NOT, addresses
Table 193. Pin interrupt registers for edge- and
enable) register (IENF, address 0x4008 7010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
set register (SIENF, address 0x4008 7014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
clear register (CIENF, address 0x4008 7018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
0x4008 701C) bit description . . . . . . . . . . . . 255
0x4008 7020) bit description . . . . . . . . . . . . . 255
7024) bit description . . . . . . . . . . . . . . . . . . . 256
addresses 0x4008 8000 (GROUP0 INT) and
0x4008 9000 (GROUP1 INT)) bit description 256
(PORT_POL, addresses 0x4008 8020
(PORT_POL0) to 0x4008 803C (PORT_POL7)
(GROUP0 INT) and 0x4008 9020 (PORT_POL0)
to 0x4008 903C (PORT_POL7) (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 257
(PORT_ENA, addresses 0x4008 8040
(PORT_ENA0) to 0x4008 805C (PORT_ENA7)
(GROUP0 INT) and 0x4008 9040 (PORT_ENA0)
to 0x4008 905C (PORT_ENA7) (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 257
0x400F 4000 (B0) to 0x400F 00FC (B255)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
0x400F 5000 (W0) to 0x400F 13FC (W255)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
0x400F 6000 (DIR0) to 0x400F 601C (DIR7)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
0x400F 6080 (MASK0) to 0x400F 609C (MASK7))
bit description . . . . . . . . . . . . . . . . . . . . . . . . 258
6100 (PIN0) to 0x400F 611C (PIN7)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
0x400F 6180 (MPIN0) to 0x400F 619C (MPIN7))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 259
6200 (SET0) to 0x400F 621C (SET7)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6280 (CLR0) to 0x400F 629C (CLR7)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
0x400F 6300 (NOT0) to 0x400F 632C (NOT7)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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