LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1160

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
36.6.3.2
36.6.3.3
36.6.3.4
36.6.3.5
36.6.3.6
36.6.3.7
36.6.3.8
36.6.4
36.6.4.1
36.7
36.7.1
36.7.2
36.7.2.1
36.7.2.2
36.7.2.3
36.7.2.4
36.7.2.4.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 839
36.7.2.4.2 Loop-back mode. . . . . . . . . . . . . . . . . . . . . . 840
36.7.2.4.3 Loop-back mode combined with Silent mode 840
36.7.2.4.4 Basic mode. . . . . . . . . . . . . . . . . . . . . . . . . . 841
36.7.2.4.5 Software control of pin CAN_TXD . . . . . . . . 841
Chapter 37: LPC18xx I2C-bus interface
37.1
37.2
37.3
37.4
37.5
37.5.1
37.6
37.7
37.7.1
37.7.2
37.7.3
37.7.4
37.7.5
37.7.5.1
37.7.6
37.7.7
37.7.7.1
37.7.7.2
37.7.8
37.7.9
37.7.10
37.8
37.8.1
37.8.2
37.8.3
37.8.4
37.9
37.9.1
37.9.2
37.9.3
37.9.4
37.9.5
<Document ID>
User manual
Functional description . . . . . . . . . . . . . . . . . 837
How to read this chapter . . . . . . . . . . . . . . . . 853
Basic configuration . . . . . . . . . . . . . . . . . . . . 853
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 854
General description . . . . . . . . . . . . . . . . . . . . 854
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 855
Register description . . . . . . . . . . . . . . . . . . . 855
I
I
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 865
C implementation and operation . . . . . . . . 868
CAN transmission request 2 register . . . . . . 834
CAN new data 1 register. . . . . . . . . . . . . . . . 835
CAN new data 2 register . . . . . . . . . . . . . . . 835
CAN interrupt pending 1 register . . . . . . . . . 835
CAN interrupt pending 2 register . . . . . . . . . 836
CAN message valid 1 register . . . . . . . . . . . 836
CAN message valid 2 register . . . . . . . . . . . 836
CAN timing register . . . . . . . . . . . . . . . . . . . 837
CAN clock divider register . . . . . . . . . . . . . . 837
C_CAN controller state after reset . . . . . . . . 837
C_CAN operating modes . . . . . . . . . . . . . . . 838
Software initialization . . . . . . . . . . . . . . . . . . 838
CAN message transfer . . . . . . . . . . . . . . . . . 838
Disabled Automatic Retransmission (DAR) . 839
Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . 839
I
I
I
I
I
I
Selecting the appropriate I
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
I
I
Interrupt in Monitor mode . . . . . . . . . . . . . . . 863
Loss of arbitration in Monitor mode . . . . . . . 863
I
I
I
Master Transmitter mode . . . . . . . . . . . . . . . 865
Master Receiver mode . . . . . . . . . . . . . . . . . 866
Slave Receiver mode . . . . . . . . . . . . . . . . . . 867
Slave Transmitter mode . . . . . . . . . . . . . . . . 868
Input filters and output stages. . . . . . . . . . . . 869
Address Registers, ADR0 to ADR3 . . . . . . . 870
Address mask registers, MASK0 to MASK3. 870
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 870
Shift register, DAT. . . . . . . . . . . . . . . . . . . . . 870
2
2
2
2
2
2
2
2
2
2
2
C Fast-mode Plus . . . . . . . . . . . . . . . . . . . 855
C Control Set register. . . . . . . . . . . . . . . . . 857
C Status register. . . . . . . . . . . . . . . . . . . . . 859
C Data register . . . . . . . . . . . . . . . . . . . . . 859
C Slave Address register 0 . . . . . . . . . . . . 860
C SCL HIGH and LOW duty cycle registers 860
C Control Clear register . . . . . . . . . . . . . . 861
C Monitor mode control register. . . . . . . . . 862
C Slave Address registers . . . . . . . . . . . . . 863
C Data buffer register . . . . . . . . . . . . . . . . . 864
C Mask registers . . . . . . . . . . . . . . . . . . . . 864
2
C data rate and duty
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
36.7.3
36.7.3.1
36.7.3.2
36.7.3.3
36.7.3.4
36.7.3.4.1 Reception of a data frame . . . . . . . . . . . . . . 845
36.7.3.4.2 Reception of a remote frame . . . . . . . . . . . . 845
36.7.3.5
36.7.3.6
36.7.3.7
36.7.3.8
36.7.3.9
36.7.3.10 Configuration of a FIFO buffer . . . . . . . . . . . 848
36.7.3.10.1 Reception of messages with FIFO buffers. 848
36.7.3.10.2 Reading from a FIFO buffer . . . . . . . . . . . . 848
36.7.4
36.7.5
36.7.5.1
37.9.6
37.9.7
37.9.8
37.9.9
37.9.10
37.10
37.10.1
37.10.2
37.10.3
37.10.4
37.10.5
37.10.5.1 STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . . 886
37.10.5.2 STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . . 886
37.10.6
37.10.6.1 Simultaneous Repeated START conditions from
37.10.6.2 Data transfer after loss of arbitration . . . . . . 888
37.10.6.3 Forced access to the I
37.10.6.4 I
37.10.6.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
37.10.7
37.10.8
37.10.9
37.10.10 The state service routines . . . . . . . . . . . . . . 890
37.10.11 Adapting state services to an application. . . 890
37.11
37.11.1
37.11.2
37.11.3
37.11.4
37.11.5
37.11.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 891
37.11.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 891
Details of I
Software example . . . . . . . . . . . . . . . . . . . . . 890
CAN message handler . . . . . . . . . . . . . . . . 842
Management of message objects . . . . . . . . 843
Data Transfer between IFx Registers and the
Message RAM . . . . . . . . . . . . . . . . . . . . . . . 844
Transmission of messages between the shift
registers in the CAN core and the Message buffer
844
Acceptance filtering of received messages . 844
Receive/transmit priority . . . . . . . . . . . . . . . 845
Configuration of a transmit object . . . . . . . . 845
Updating a transmit object . . . . . . . . . . . . . . 846
Configuration of a receive object . . . . . . . . . 846
Handling of received messages. . . . . . . . . . 847
Interrupt handling . . . . . . . . . . . . . . . . . . . . . 849
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Bit time and bit rate . . . . . . . . . . . . . . . . . . . 851
Arbitration and synchronization logic . . . . . . 870
Serial clock generator . . . . . . . . . . . . . . . . . 871
Timing and control . . . . . . . . . . . . . . . . . . . . 872
Control register, CONSET and CONCLR . . 872
Status decoder and status register. . . . . . . . 872
Master Transmitter mode . . . . . . . . . . . . . . . 873
Master Receiver mode. . . . . . . . . . . . . . . . . 877
Slave Receiver mode. . . . . . . . . . . . . . . . . . 880
Slave Transmitter mode . . . . . . . . . . . . . . . . 884
Miscellaneous states . . . . . . . . . . . . . . . . . . 886
Some special cases . . . . . . . . . . . . . . . . . . . 887
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 887
889
I
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 890
I
Initialization routine . . . . . . . . . . . . . . . . . . . 890
Start Master Transmit function . . . . . . . . . . . 890
Start Master Receive function . . . . . . . . . . . 891
I
Non mode specific states. . . . . . . . . . . . . . . 891
2
2
2
2
C-bus obstructed by a LOW level on SCL or SDA
C state service routines . . . . . . . . . . . . . . . 889
C interrupt service . . . . . . . . . . . . . . . . . . . 890
C interrupt routine . . . . . . . . . . . . . . . . . . . 891
Chapter 43: Supplementary information
2
C operating modes . . . . . . . . . . 872
2
C-bus. . . . . . . . . . . . 888
UM10430
© NXP B.V. 2011. All rights reserved.
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