LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 770

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

34.1 How to read this chapter
34.2 Basic configuration
34.3 Features
34.4 General description
<Document ID>
User manual
The SSP0/1 controllers are available on all LPC18xx parts.
The SSP0/1 are configured as follows:
Table 712. SSP0/1 clocking and power control
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC18xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.
Clock to SSP0 register interface
SSP0 peripheral clock (PCLK)
Clock to SSP1 register interface
SSP1 peripheral clock (PCLK)
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UM10430
Chapter 34: LPC18xx SSP0/1
Rev. 00.13 — 20 July 2011
See
The SSP0/1 are reset by the SSP0/1_RST (reset #50/51).
The SSP0/1 interrupts are connected to slots # 22/23 in the NVIC.
For connecting the SSP0/1 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see
in the DMA Channel Configuration registers
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Supports master or slave operation.
Eight-frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
Table 712
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_M3_CLK
BASE_SSP0_CLK
BASE_M3_CLK
BASE_SSP1_CLK
Table
(Section
35) and enable the GPDMA channel
16.6.20).
Branch clock
CLK_M3_SSP0
CLK_APB0_SSP0
CLK_M3_SSP1
CLK_APB2_SSP1
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
150 MHz
150 MHz
150 MHz
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