LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 885

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 823. Slave Transmitter mode
<Document ID>
User manual
Status
Code
(STAT)
0xA8
0xB0
0xB8
0xC0
0xC8
Status of the I
and hardware
Own SLA+R has been
received; ACK has
been returned.
Arbitration lost in
SLA+R/W as master;
Own SLA+R has been
received, ACK has
been returned.
Data byte in DAT has
been transmitted;
ACK has been
received.
Data byte in DAT has
been transmitted;
NOT ACK has been
received.
Last data byte in DAT
has been transmitted
(AA = 0); ACK has
been received.
2
C-bus
Application software response
To/From DAT
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
Load data byte
No DAT action or
No DAT action or
No DAT action or
No DAT action
No DAT action or
No DAT action or
No DAT action or
No DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
To CON
STA STO SI
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
0
1
0
1
0
1
0
1
0
1
0
1
0
01
Chapter 37: LPC18xx I2C-bus interface
Next action taken by I
Last data byte will be transmitted and
ACK bit will be received.
Data byte will be transmitted; ACK will be
received.
Last data byte will be transmitted and
ACK bit will be received.
Data byte will be transmitted; ACK bit will
be received.
Last data byte will be transmitted and
ACK bit will be received.
Data byte will be transmitted; ACK bit will
be received.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR.0 = logic 1. A START condition will
be transmitted when the bus becomes
free.
UM10430
© NXP B.V. 2011. All rights reserved.
2
C hardware
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