LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 966
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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User manual
42.2.6.5 Event status register
Table 909. Event set enable register (SET_EN - address 0x4004 4FDC) bit description
Table 910. Interrupt status register (STATUS - address 0x4004 4FE0) bit description
Bit
14
15
16
18:17
19
31:20
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18:17
19
31:20
Symbol
TIM6_SETEN
QEI_SETEN
TIM14_SETEN
-
RESET_SETEN
-
Symbol
WAKEUP0_ST A 1 in this bit shows that the WAKEUP0 event has been raised. -
WAKEUP1_ST A 1 in this bit shows that the WAKEUP1 event has been raised. -
WAKEUP2_ST A 1 in this bit shows that the WAKEUP2 event has been raised. -
WAKEUP3_ST A 1 in this bit shows that the WAKEUP3 event has been raised. -
ATIMER_ST
RTC_ST
BOD_ST
WWDT_ST
ETH_ST
USB0_ST
USB1_ST
-
CAN_ST
TIM2_ST
TIM6_ST
QEI_ST
TIM14_ST
-
RESET_ST
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
A 1 in this bit shows that the ATIMER event has been raised.
A 1 in this bit shows that the RTC event has been raised.
A 1 in this bit shows that the BOD event has been raised.
A 1 in this bit shows that the WWDT event has been raised.
A 1 in this bit shows that the ETHERNET event has been raised. -
A 1 in this bit shows that the USB0 event has been raised.
A 1 in this bit shows that the USB1 event has been raised.
Reserved.
A 1 in this bit shows that the C_CAN event has been raised.
A 1 in this bit shows that the combined timer 2 output event has
been raised.
A 1 in this bit shows that the combined timer 6 output event has
been raised.
A 1 in this bit shows that the QEI event has been raised.
A 1 in this bit shows that the combined timer 14 output event has
been raised.
Reserved.
A 1 in this bit shows that the <tbd> event has been raised.
Reserved.
Description
Writing a 1 to this bit sets the event enable bit 14 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 15 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 16 in the
ENABLE register.
Reserved.
Writing a 1 to this bit sets the event enable bit 19 in the
ENABLE register.
Reserved.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
966 of 1164
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