LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 431

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.12.1 High-frequency interrupts
20.10.12.2 Low-frequency interrupts
20.10.12.3 Error interrupts
20.10.12 Servicing interrupts
Table 354. Device error matrix
The interrupt service routine must consider that there are high-frequency, low-frequency
operations, and error operations and order accordingly.
High frequency interrupts in particular should be handed in the order below. The most
important of these is listed first because the DCD must acknowledge a setup buffer in the
timeliest manner possible.
Table 355. High-frequency interrupt events
[1]
The low frequency events include the following interrupts. These interrupt can be handled
in any order since they don’t occur often in comparison to the high-frequency interrupts.
Table 356. Low-frequency interrupt events
Error interrupts will be least frequent and should be placed last in the interrupt service
routine.
Error
Overflow
ISO packet error
ISO fulfillment
error
Execution order
1a
1b
2
Interrupt
Port change
Sleep enable (Suspend)
Reset Received
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during
the Interrupt Service Routine.
All information provided in this document is subject to legal disclaimers.
Direction
Rx
Rx
Both
Interrupt
USB interrupt:
ENDPTSETUPSTATUS
[1]
USB interrupt:
ENDPTCOMPLETE
SOF interrupt
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Packet type
Any
ISO
ISO
[1]
Action
Copy contents of setup buffer and acknowledge
setup packet (as indicated in
Process setup packet according to USB 2.0 Chapter
9 or application specific protocol.
Handle completion of dTD as indicated in
Section
Action as deemed necessary by application. This
interrupt may not have a use in all applications.
Action
Change software state information.
Change software state information. Low power
handling as necessary.
Change software state information. Abort
pending transfers.
20.10.10.
Data buffer error
bit
1
0
0
Section
UM10430
© NXP B.V. 2011. All rights reserved.
0
Transaction
error bit
1
1
20.10.10).
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