LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 420

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.6.2 Priming receive endpoints
20.10.7 Interrupt/bulk endpoint operational model
transaction starts. The FIFO must be sized to account for the maximum latency that can
be incurred by the system memory bus. On the LPC18xx, 128 x 36 bit dual port memory
FIFOs are used for each IN endpoint.
Priming receive endpoints is identical to priming of transmit endpoints from the point of
view of the DCD. At the device controller the major difference in the operational model is
that there is no data movement of the leading packet data simply because the data is to
be received from the host. Note as part of the architecture, the FIFO for the receive
endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of
the RX FIFO does not scale with the number of endpoints.
The behaviors of the device controller for interrupt and bulk endpoints are identical. All
valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the
endpoint had been primed. Once the endpoint has been primed, data delivery will
commence.
A dTD will be retired by the device controller when the packets described in the transfer
descriptor have been completed. Each dTD describes N packets to be transferred
according to the USB Variable Length transfer protocol. The formula and table on the
following page describe how the device controller computes the number and length of the
packets to be sent/received by the USB vary according to the total number of bytes and
maximum packet length.
Table 349. Variable length transfer protocol example (ZLT = 0)
Table 350. Variable length transfer protocol example (ZLT = 1)
Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
TX-dTD is complete when all packets described dTD were successfully transmitted.Total
bytes in dTD will equal zero when this occurs.
Bytes (dTD)
511
512
512
Bytes (dTD)
511
512
512
With Zero Length Termination (ZLT) = 0
With Zero Length Termination (ZLT) = 1
N = INT(Number Of Bytes/Max. Packet Length) + 1
N = MAXINT(Number Of Bytes/Max. Packet Length)
Max Packet
Length (dQH)
256
256
512
All information provided in this document is subject to legal disclaimers.
Max Packet Length
(dQH)
256
256
512
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
N
2
2
1
N
2
3
2
P1
256
256
512
P1
256
256
512
P2
255
256
-
P2
255
256
0
UM10430
© NXP B.V. 2011. All rights reserved.
P3
-
-
-
P3
-
0
-
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