LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 663

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.8.5 External event counting (Counter mode)
26.8.6 Three-phase DC mode
If a channel’s HNF bit in the CAPCON register is set to enable “noise filtering”, a selected
edge on an MCI pin starts the dead-time counter for that channel, and the capture event
actions described below are delayed until the dead-time counter reaches 0. This function
is targeted specifically for performing three-phase brushless DC motor control with Hall
sensors.
A capture event on a channel (possibly delayed by HNF) causes the following:
If a channel’s MODE bit is 1 in CNTCON, its TC is incremented by rising and/or falling
edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM
functions and capture functions are unaffected.
The three-phase DC mode is selected by setting the DCMODE bit in the CON register.
In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Each MCO output is masked by a bit in the current commutation pattern register CP. If a
bit in the CP register is 0, its output pin has the logic level for the passive state of output
MCOA0. The polarity of the off state is determined by the POLA0 bit.
All MCO outputs that have 1 bits in the CP register are controlled by the internal MCOA0
signal.
The three MCOB output pins are inverted when the INVBDC bit is 1 in the CON register.
This feature accommodates bridge-drivers that have active-low inputs for the low-side
switches.
The CP register is implemented as a shadow register pair, so that changes to the active
communication pattern occur at the beginning of a new PWM cycle. See
26.8.2
Figure 78
and 3 in the CP register (corresponding to outputs MCOB1 and MCOB0) are set to 0 so
that these outputs are masked and in the off state. Their logic level is determined by the
POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set to
0 (logic level not inverted) so that the B output have the same polarity as the A outputs.
Note that this mode differs from other modes in that the MCOB outputs are not the
opposite of the MCOA outputs.
In the situation shown in
means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.
•
•
•
The current value of the TC is stored in the Capture register (CAP).
If the channel’s capture event interrupt is enabled (see
interrupt flag is set.
If the channel’s RT bit is set in the CAPCON register, enabling reset on a capture
event, the input event has the same effect as matching the channel’s TC to its LIM
register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned
mode as described in
for more about writing and reading such registers.
shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
26.7.4
78, bits 0, 2, 4, and 5 in the CP register are set to 1. That
and 26.8.1.
Table
562), the capture event
UM10430
© NXP B.V. 2011. All rights reserved.
26.7.4
and
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