LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 332

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.7 Dynamic Memory Precharge Command Period register
19.7.8 Dynamic Memory Active to Precharge Command Period register
See
command lines.
Table 271. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG - address
The DynamicTRP register enables you to program the precharge command period, tRP.
This register must only be modified during system initialization. This value is normally
found in SDRAM data sheets as tRP. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 272. Dynamic Memory Precharge Command Period register (DYNAMICRP - address
The DynamicTRAS register enables you to program the active to precharge command
period, tRAS. It is recommended that this register is modified during system initialization,
or when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tRAS. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Bit
1:0
31:2
Bit
3:0
31:4
Section 19.4.4
Symbol
-
Symbol
-
RD
tRP
0x4000 5028) bit description
0x4000 5030) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
-
Description
Precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
to
Section 19.4.12
Rev. 00.13 — 20 July 2011
Read data strategy.
Clock out delayed strategy, using CLKOUT (command not
delayed, clock out delayed). POR reset value.
Command delayed strategy, using CCLKDELAY (command
delayed, clock out not delayed).
Command delayed strategy plus one clock cycle, using
CCLKDELAY (command delayed, clock out not delayed).
Command delayed strategy plus two clock cycles, using
CCLKDELAY (command delayed, clock out not delayed).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
for programming delay value for address, data, and
UM10430
© NXP B.V. 2011. All rights reserved.
332 of 1164
Reset
value
0x0
-
Reset
value
0xF
-