LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 855

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.6 Pin description
37.7 Register description
Table 800. Register overview: I
<Document ID>
User manual
Name
CONSET
STAT
DAT
ADR0
SCLH
SCLL
CONCLR
37.5.1 I
Access Address
R/W
RO
R/W
R/W
R/W
R/W
WO
Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I
products which NXP Semiconductors is now providing.
In order to use Fast-Mode Plus, the I
register in the SYSCON block (see
Table 799. I
The I
or Fast-mode Plus.
Pin
SDA0
SCL0
SDA1
SCL1
2
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
C Fast-mode Plus
2
C-bus pins must be configured through SYSCON registers for Standard/ Fast-mode
2
C0 (base address 0x400A 1000)
2
C-bus pin description
Description
I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
no effect on the corresponding bit in the I
I2C Status Register. During I
status codes that allow software to determine the next action needed.
I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
SCH Duty Cycle Register High Half Word. Determines the high time of
the I
SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
generated by an I
I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
has no effect on the corresponding bit in the I
Type
Input/Output
Input/Output
Input/Output
Input/Output
All information provided in this document is subject to legal disclaimers.
2
2
C clock.
C clock. SCLL and SCLH together determine the clock frequency
Rev. 00.13 — 20 July 2011
2
2
C interface in slave mode, and is not used in master
C master and certain times used in slave mode.
Description
I
compliance).
I
compliance).
I
only).
I
only).
2
2
2
2
C data input/output. Open-drain output (for I
C clock input/output. Open-drain output (for I
C Serial Data. Uses standard I/O pins (Fast-mode
C Serial Clock. Uses standard I/O pins (Fast-mode
Table
2
C pins must be properly configured in the SFSI2C0
2
2
C control register is set. Writing a zero has
C control register is cleared. Writing a zero
2
C operation, this register provides detailed
205).
Chapter 37: LPC18xx I2C-bus interface
2
C control register.
2
C control register.
UM10430
© NXP B.V. 2011. All rights reserved.
2
2
C-bus
C-bus
2
C-bus
855 of 1164
Reset
value
0x00
0xF8
0x00
0x00
0x04
0x04
-
[1]