LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 813

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 753. CAN control registers (CNTL, address 0x400E 2000 (C_CAN0) and 0x400A 4000
Remark: The busoff recovery sequence (see CAN Specification Rev. 2.0 ) cannot be
shortened by setting or resetting the INIT bit. If the device goes into busoff state, it will set
INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device will
then wait for 129 occurrences of Bus Idle (129  11 consecutive HIGH/recessive bits)
before resuming normal operations. At the end of the busoff recovery sequence, the Error
Management Counters will be reset.
During the waiting time after the resetting of INIT, each time a sequence of 11
HIGH/recessive bits has been monitored, a Bit0Error code is written to the Status Register
CANSTAT, enabling the CPU to monitor the proceeding of the busoff recovery sequence
and to determine whether the CAN bus is stuck at LOW/dominant or continuously
disturbed.
Bit
5
6
7
31:8
Symbol Value
DAR
CCE
TEST
-
(C_CAN1)) bit description
…continued
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Test mode enable
Description
Disable automatic retransmission
Automatic retransmission of disturbed
messages enabled.
Automatic retransmission disabled.
Configuration change enable
The CPU has no write access to the bit timing
register.
The CPU has write access to the CANBT
register while the INIT bit is one.
Normal operation.
Test mode.
reserved
Chapter 36: LPC18xx C_CAN
Reset
value
0
0
0
-
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/W
R/W
R/W
-
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