LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 26

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
3.3.3 Boot image format
AES capable products with a programmed AES key will always boot from a secure image
and use CMAC authentication. A secure image should always include a header.
Non-AES capable products may boot from an image with header or execute directly from
the boot source (when the boot source is memory mapped; SPIFI or EMC). When no valid
header is found then the CPU will try to execute code from the first location of the memory
mapped boot source. The user should take care that this location contains executable
code, otherwise a hard fault exception will occur. This exception jumps to a while(1) loop.
The image must be preceded by a header that has the layout described in
Non-encrypted images may omit the header.
Table 9.
[1]
[2]
[3]
Address
5:0
7:6
13:8
15:14
31:16
95:32
127:96
Can only be active if device is AES capable, else is considered an invalid image.
16 extra bytes are required for the header bytes.
The image size should be set to no more than the size of the SRAM located at 0x1000 0000.
Image header
All information provided in this document is subject to legal disclaimers.
Name
AES_ACTIVE
HASH_ACTIVE
reserved
AES_CONTROL
HASH_SIZE
HASH_VALUE
reserved
Rev. 00.13 — 20 July 2011
[3]
[1]
[1]
Description
AES encryption active
0x25 (100101): AES encryption active
0x1A (011010): AES encryption not active
else: invalid image
Indicates whether a hash is used:
00: CMAC hash is used, value is
HASH_VALUE
01: reserved
10: reserved
11: no hash is used
when AES encryption is active, that the
AES_ACTIVE field, after AES encryption, is
not equal to the value 0x1A (AES encryption
not active)
Size of the part of the image over which the
hash value is calculated in number of 512
Byte frames. Also size of image copied to
internal SRAM at boot time.
Hash size = 16
bytes of the image (starting right from the
header) as indicated by HASH_SIZE. The
value is truncated to the 64 MSB.
11...11 (binary)
11...11 (binary)
These 2 bits can be set to a value such that
CMAC hash value calculated over the first
[2]
+ HASH_SIZE x 512 Byte.
Chapter 3: LPC18xx Boot ROM
UM10430
© NXP B.V. 2011. All rights reserved.
Table
size [bits]
6
2
6
2
16
64
32
9.
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