LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1059

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.8.4.4 GPIO port output set register (SET)
Table 985. GPIO port pin value register (PIN0 to PIN0 - addresses 0x400F 0014 to 0x400F
Aside from the 32-bit long and word only accessible PIN register, every GPIO port can
also be controlled via two byte and one half-word accessible register listed in
Next to providing the same functions as the PIN register, these additional registers allow
easier and faster access to the physical port pins.
Table 986. GPIO port pin value byte and half-word accessible register description
SET is used to produce a HIGH level output at the port pins configured as GPIO in output
mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no
effect. If any pin is configured as an input or a secondary function, writing 1 to the
corresponding bit in the SET has no effect.
Reading SET returns the value of this register as determined by previous writes to SET
and CLR (or PIN as noted above). This value does not reflect the effect of any outside
world influence on the I/O pins.
Access to a port pin via the SET register is masked by the corresponding bit of the MASK
register (see
Bit
15:0
31:16
Generic
register
name
PINn_0
PINn_1
PINn_L
Symbol
VALPIN
-
0094) bit description
Description
GPIO port x pin value register
0. Bit 0 corresponds to pin
GPIOx_0... bit 7 to pin
GPIOx_7.
GPIO port x pin value register
1. Bit 0 corresponds to pin
GPIOx_8... bit 7 to pin
GPIOx_15.
GPIO port x pin value Lower
half-word register. Bit 0 register
corresponds to pin GPIOx_0...
bit 15 to pin GPIOx_15.
Section
All information provided in this document is subject to legal disclaimers.
Description
GPIO output value bits. Bit 0 corresponds to pin GPIOx_0, bit 15
corresponds to pin GPIOx_15. Only bits also set to 0 in the MASKn
register are affected by a write or show the pin’s actual logic state.
0 = Reading a 0 indicates that the port pin’s current state is LOW.
Writing 0 sets the output register value to LOW.
1 = Reading a 1 indicates that the port pin’s current state is HIGH.
Writing a 1 sets the output register value to HIGH.
Reserved.
42.8.4.2).
Rev. 00.13 — 20 July 2011
Register
length in bits
/access
8 (byte)/
R/W
8 (byte)/
R/W
16
(half-word)/
R/W
Reset
value
0x00
0x00
0x0000 PIN0_L - 0x400F 0014
Port x register name -
address
PIN0_0 - 0x400F 0014
PIN1_0 - 0x400F 0034
PIN2_0 - 0x400F 0054
PIN3_0 - 0x400F 0074
PIN4_0 - 0x400F 0094
PIN0_1 - 0x400F 0015
PIN1_1 - 0x400F 0035
PIN2_1 - 0x400F 0055
PIN3_1 - 0x400F 0075
PIN4_1 - 0x400F 0095
PIN1_L - 0x400F 0034
PIN2_L - 0x400F 0054
PIN3_L - 0x400F 0074
PIN4_L - 0x400F 0094
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Table
1059 of 1164
Reset
value
0x0
-
986.