LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 28

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
3.3.4.2 UART boot mode
Figure 11
happens only if the boot mode is set accordingly (see boot modes
As illustrated in
Auto baud is active; boot waits until 0x3F is received and responds with “OK”. This should
be followed by the header and image. The boot ROM doesn't implement any flow control
or any handshake mechanisms during file transfer.
Fig 10. CMAC generation
•
•
•
•
Baudrate = 115200 (UART divisor registers are programmed assuming a 12 MHz
clock frequency).
Data bits = 8.
Parity = None.
Stop bits = 1.
details the boot-flow steps of the UART boot mode. The execution of this mode
AES
All information provided in this document is subject to legal disclaimers.
Figure
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Rev. 00.13 — 20 July 2011
11, configure the UART with the following settings:
AES
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AES
M*
+
n
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Chapter 3: LPC18xx Boot ROM
1
MSB
64
Table 7
UM10430
© NXP B.V. 2011. All rights reserved.
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