LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 429

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.11.3 Executing a transfer descriptor
20.10.11.4 Transfer completion
To safely add a dTD, the DCD must follow this procedure which will handle the event
where the device controller reaches the end of the dTD list at the same time a new dTD is
being added to the end of the list.
Determine whether the link list is empty: Check DCD driver to see if pipe is empty (internal
representation of linked-list should indicate if any packets are outstanding).
Link list is empty
Link list is not empty
After a dTD has been initialized and the associated endpoint primed the device controller
will execute the transfer upon the host-initiated request. The DCD will be notified with a
USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the
endpoint complete register to find when the dTD had been executed. After a dTD has
been executed, DCD can check the status bits to determine success or failure.
Remark: Multiple dTD can be completed in a single endpoint complete notification. After
clearing the notification, DCD must search the dTD linked list and retire all dTDs that have
finished (Active bit cleared).
By reading the status fields of the completed dTDs, the DCD can determine if the
transfers completed successfully. Success is determined with the following combination of
status bits:
1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation.
2. Clear active and halt bits in dQH (in case set from a previous error).
3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME.
1. Add dTD to end of the linked list.
2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE.
3. Set ATDTW bit in USBCMD register to ‘1’.
4. Read correct status bit in ENDPTSTAT. (Store in temp variable for later).
5. Read ATDTW bit in USBCMD register.
6. Write ATDTW bit in USBCMD register to ‘0’.
7. If status bit read in step 4 (ENDPSTAT reg) indicates endpoint priming is DONE
8. If status bit read in step 4 is 0 then go to Linked list is empty: Step 1.
Active = 0
Halted = 0
Transaction Error = 0
Data Buffer Error = 0
– If ‘0’ go to step 3.
– If ‘1’ continue to step 6.
(corresponding ERBRx or ETBRx is one): DONE.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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