LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 973

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.3.4.4 ARM Cortex-M3 memory mapping register
42.3.4.5 CREG5 control register
42.3.4.6 DMA muxing register
Table 919. Memory mapping register (M3MEMMAP, address 0x4004 3100) bit description
Table 920. CREG5 control register (CREG5, address 0x4004 3118) bit description
This register controls which set of peripherals is connected to the DMA controller (see
Table
Table 921. DMA muxing register (DMAMUX, address 0x4004 311C) bit description
Bit
11:0
31:12
Bit
4:0
5
6
7
8
31:9
Bit
1:0
3:2
5:4
195).
Symbol
DMAMUXCH0
DMAMUXCH1
DMAMUXCH2
Symbol
M3MAP
Symbol
-
-
M3TAPSEL
-
OTPJTAG
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Description
Reserved.
Reserved.
Selects tap access to M3
Reserved. This bit must always be set to 0.
JTAG access to OTP
Reserved.
Description
Reserved
this is the 32 kB ROM address - this is the
shadow address when accessing memory at
address 0x0000 0000
Description
selects DMA to peripheral connection for
DMA peripheral 0:
SPIFI
Reserved
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 1:
Timer 0, match channel 0
USART0 transmit
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 2:
Timer 0, match channel 1
USART0 receive
Reserved
Reserved
Chapter 42: Appendix
UM10430
Reset
value
0x000
0x1040
0000
© NXP B.V. 2011. All rights reserved.
Reset
value
-
0
0
0
0
-
Reset
value
0
0
0
Access
-
-
R/W
-
R/W
-
Access
-
R/W
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Access
R/W
R/W
R/W