LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 983

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.6.1 Frequency monitor register
Table 930. Register overview: CGU (base address 0x4005 0000)
The CGU can report the relative frequency of any operating clock. The clock to be
measured must be selected by software, while the fixed-frequency IRC clock fref is used
as the reference frequency. A 14-bit counter then counts the number of cycles of the
measured clock that occur during a user-defined number of reference-clock cycles. When
the MEAS bit is set, the measured-clock counter is reset to 0 and counts up, while the
9-bit reference-clock counter is loaded with the value in RCNT and then counts down
Name
-
OUTCLK_3_CTRL
OUTCLK_4_CTRL
OUTCLK_5_CTRL
-
OUTCLK_7_CTRL
OUTCLK_8_CTRL
OUTCLK_9_CTRL
OUTCLK_10_CTRL
OUTCLK_11_CTRL
-
OUTCLK_13_CTRL
OUTCLK_14_CTRL
OUTCLK_15_CTRL
OUTCLK_16_CTRL
OUTCLK_17_CTRL
OUTCLK_18_CTRL
OUTCLK_19_CTRL
OUTCLK_20_CTRL
OUTCLK_21_CTRL
to
OUTCLK_25_CTRL
All information provided in this document is subject to legal disclaimers.
Access Address
-
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 00.13 — 20 July 2011
0x070
0x074
0x07C
0x080
offset
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x078
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C to
0x0AC
Description
Reserved
Output stage 3 control register for
base clock BASE_USB1_CLK
Output stage 4 control register for
base clock BASE_M3_CLK
Output stage 5 control register for
base clock BASE_SPIFI_CLK
Reserved
Output stage 7 control register for
base clock BASE_PHY_RX_CLK
Output stage 8 control register for
base clock BASE_PHY_TX_CLK
Output stage 9 control register for
base clock BASE_APB1_CLK
Output stage 10 control register for
base clock BASE_APB3_CLK
Output stage 11 control register for
base clock BASE_LCD_CLK
Reserved
Output stage 13 control register for
base clock BASE_SDIO_CLK
Output stage 14 control register for
base clock BASE_SSP0_CLK
Output stage 15 control register for
base clock BASE_SSP1_CLK
Output stage 16 control register for
base clock BASE_UART0_CLK
Output stage 17 control register for
base clock BASE_UART1_CLK
Output stage 18 control register for
base clock BASE_UART2_CLK
Output stage 19 control register for
base clock BASE_UART3_CLK
Output stage 20 control register for
base clock BASE_OUT_CLK
Reserved output stages
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
-
-
-
-
0x0100 0000
0x0800 0800
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
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