LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 67

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 17. CGU and CCU0/1 block diagram
ENET_RX_CLK
ENET_TX_CLK
GP_CLK
RTCX1
RTCX2
XTAL1
XTAL2
CGU
The CGU selects the inputs to the clock generators from multiple clock sources, controls
the clock generation, and routes the outputs of the clock generators through the clock
source bus to the output stages. Each output stage provides an independent clock source
and corresponds to one of the base clocks for the LPC18xx. See
description of each base clock and
clock.
The CGU contains four types of clock generators:
1. External clock inputs and internal clocks: The external clock inputs are the Ethernet
2. Crystal oscillator: The crystal oscillator is controlled by the CGU. The input to the
3. PLLs: PLL0 (USB0), PLL0 (audio), and PLL1 are controlled by the CGU. Each PLL
4. Integer dividers: Each of the five integer dividers can select one input from the clock
PHY clocks and the general purpose input clock GP_CLKIN. The clocks from the
internal oscillators are the IRC and the 32 kHz oscillator output clocks. These clock
generators have no selectable inputs from the clock source bus and provide one clock
output each to the clock source bus.
crystal oscillator are the XTAL pins. The crystal oscillator creates one output to the
clock source bus.
can select one input from the clock source bus and provides one output to the clock
source bus. The input to the PLLs can be selected from all external and internal
clocks and oscillators, from the other PLLs, and from the outputs of any of the integer
dividers (see
source bus and creates one divided output clock to the clock source bus. The input to
all integer dividers can be selected from all external and internal clocks and
oscillators, and from all three PLLs. In addition, the output of the first integer divider
can be selected as an input to all other integer dividers (see
CRYSTAL OSC
32 kHz OSC
12 MHz IRC
All information provided in this document is subject to legal disclaimers.
(AUDIO)
(USB0)
PLL0
Table
PLL0
PLL1
Rev. 00.13 — 20 July 2011
45). One PLL0 cannot select the other PLL0 as input.
IDIVB
IDIVC
IDIVC
IDIVE
IDIVA
/256
/16
/16
/16
/4
OUTCLK1, 3 - 6, 9 - 10
(BASE_xxx_CLK)
BASE_SAFE_CLK
OUTCLK12 - 19
(BASE_xxx_CLK)
Table 46
OUTCLK11
OUTCLK20
OUTCLK25
OUTCLK26
OUTCLK27
OUTCLK7
OUTCLK8
Chapter 9: LPC18xx Clock Generation Unit (CGU)
for the possible clock sources for each base
7
8
LCD_CLK
ENET_RX_CLK
ENET_TX_CLK
WWDT
CLKOUT
APLL
CGU_OUT0
CGU_OUT1
CCU1
CCU2
Table
Table 44
UM10430
45).
© NXP B.V. 2011. All rights reserved.
branch clocks to core
and peripherals
branch clocks to
peripherals
for a
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