LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 441

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 363. HCSPARAMS register (HCSPARAMS - address 0x4000 7104) bit description
Bit
3:0
4
7:5
11:8
15:12
16
19:17
23:20
27:24
31:28
Symbol
N_PORTS
PPC
-
N_PCC
PI
N_TT
N_CC
-
N_PTT
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Number of downstream ports. This field
specifies the number of physical
downstream ports implemented on this host
controller.
Port Power Control. This field indicates
whether the host controller implementation
includes port power control.
These bits are reserved and should be set
to zero.
Number of Ports per Companion Controller.
This field indicates the number of ports
supported per internal Companion
Controller.
Number of Companion Controller. This field
indicates the number of companion
controllers associated with this USB2.0 host
controller.
Port indicators. This bit indicates whether
the ports support port indicator control.
These bits are reserved and should be set
to zero.
Number of Ports per Transaction Translator.
This field indicates the number of ports
assigned to each transaction translator
within the USB2.0 host controller.
Number of Transaction Translators. This
field indicates the number of embedded
transaction translators associated with the
USB2.0 host controller.
These bits are reserved and should be set
to zero.
Chapter 21: LPC18xx USB1 Host/Device controller
Reset value Access
0x1
0x1
-
0x0
0x0
0x1
-
0x0
0x0
-
UM10430
© NXP B.V. 2011. All rights reserved.
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