LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 550

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.4 Line End Control register
Table 458. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description
The LE register controls the enabling of line-end signal LCDLE. When enabled, a positive
pulse, four LCDCLK periods wide, is output on LCDLE after a programmable delay, LED,
from the last pixel of each display line. If the line-end signal is disabled it is held
permanently LOW.
Bits
13
14
15
25:16
26
31:27
Symbol
IPC
IOE
-
CPL
BCD
PCD_HI
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Invert panel clock.
The IPC bit selects the edge of the panel clock on which pixel
data is driven out onto the LCD data lines.
0 = Data is driven on the LCD data lines on the rising edge of
LCDDCLK.
1 = Data is driven on the LCD data lines on the falling edge of
LCDDCLK.
Invert output enable.
This bit selects the active polarity of the output enable signal in
TFT mode. In this mode, the LCDENAB pin is used as an enable
that indicates to the LCD panel when valid display data is
available. In active display mode, data is driven onto the LCD
data lines at the programmed edge of LCDDCLK when
LCDENAB is in its active state.
0 = LCDENAB output pin is active HIGH in TFT mode.
1 = LCDENAB output pin is active LOW in TFT mode.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Clocks per line.
This field specifies the number of actual LCDDCLK clocks to the
LCD panel on each line. This is the number of PPL divided by
either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for
color passive), minus one. This must be correctly programmed in
addition to the PPL bit in the TIMH register for the LCD display to
work correctly.
Bypass pixel clock divider.
Setting this to 1 bypasses the pixel clock divider logic. This is
mainly used for TFT displays.
Upper five bits of panel clock divisor.
See description for PCD_LO, in bits [4:0] of this register.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0
0x0
-
0x0
0x0
0x0