LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 624

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 533. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1),
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<Document ID>
User manual
Name
PC
MCR
MR0
MR1
MR2
MR3
CCR
CR0
CR1
CR2
CR3
EMR
CTCR
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3))
25.7.1 Timer interrupt registers
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
R/W
R/W
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset
the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match
also clears any corresponding DMA request.
Table 534. Timer interrupt registers IR(IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000
Bit
0
1
2
3
4
5
offset
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x070
Symbol
MR0INT
MR1INT
MR2INT
MR3INT
CR0INT
CR1INT
(TIMER1), 0x400C 3000 (TIMER3), 0x400C 4000 (TIMER4)) bit description
Description
Prescale Counter. The 32 bit PC is a counter which is incremented to the
value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and controllable
through the bus interface.
Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
Match Register 0. MR0 can be enabled through the MCR to reset the TC,
stop both the TC and PC, and/or generate an interrupt every time MR0
matches the TC.
Match Register 1. See MR0 description.
Match Register 2. See MR0 description.
Match Register 3. See MR0 description.
Capture Control Register. The CCR controls which edges of the capture
inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place.
Capture Register 0. CR0 is loaded with the value of TC when there is an
event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input.
Capture Register 1. See CR0 description.
Capture Register 2. See CR0 description.
Capture Register 3. See CR0 description.
External Match Register. The EMR controls the external match pins
MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).
Count Control Register. The CTCR selects between Timer and Counter
mode, and in Counter mode selects the signal and edge(s) for counting.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
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