LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 307

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 236. Command Register (CMD, address 0x4000 402C) bit description
<Document ID>
User manual
Bit
14
15
20:16
21
Symbol
STOP_ABORT_CMD
SEND_INITIALIZATION
CARD_NUMBER
UPDATE_CLOC_REGI
STERS_ONLY
Value
0
1
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
stop abort cmd. When open-ended or predefined data transfer is in
progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of
CIU can return correctly to idle state. This is also applicable for Boot
mode transfers. To Abort boot mode, this bit should be set along with
CMD[26] = disable_boot.
Neither stop nor abort command to stop current data transfer in
progress. If abort is sent to function-number currently selected or not
in data-transfer mode, then bit should be set to 0.
Stop or abort command intended to stop current data transfer in
progress.
send initialization. After power on, 80 clocks must be sent to card for
initialization before sending any commands to card. Bit should be set
while sending first command to card so that controller will initialize
clocks before sending command to card. This bit should not be set for
either of the boot modes (alternate or mandatory).
Do not send initialization sequence (80 clocks of 1) before sending
this command.
Send initialization sequence before sending this command.
card number. Card number in use. Represents physical slot number
of card being accessed. In MMC-Ver3.3-only mode, up to 30 cards
are supported; in SD-only mode, up to 16 cards are supported.
Registered version of this is reflected on dw_dma_card_num and
ge_dma_card_num ports, which can be used to create separate DMA
requests, if needed. In addition, in SD mode this is used to mux or
demux signals from selected card because each card is interfaced to
DWC_mobile_storage by separate bus.
update clock registers only. Following register values transferred into
card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card
clocks (change frequency, truncate off or on, and set low-frequency
mode); provided in order to change clock frequency or stop clock
without having to send command to cards. During normal command
sequence, when update_clock_registers_only = 0, following control
registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT,
CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new
command sequence to card(s). When bit is set, there are no
Command Done interrupts because no command is sent to
SD_MMC_CEATA cards. registers_only.
Normal command sequence
Do not send commands, just update clock register value into card
clock domain
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0