LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 809

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
36.6 Register description
<Document ID>
User manual
Register values at reset
After a hardware reset, the registers hold the values described in
the busoff state is reset and the output TD0,1 is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
Timing of read/write operations
Remark: Reading any of the CAN registers requires two consecutive read operations
from the same location. Only the data from the second read operation are valid.
Successive read operations to the C_CAN registers must be separated by a minimum of
(CLKDIVVAL  2 + 2)  PCLK, where CLKDIVVAL is the can clock divider value and
PCLK is the peripheral clock.
Successive write operations to the C_CAN registers must be separated by a minimum of
(CLKDIVVAL  2)  PCLK, where CLKDIVVAL is the can clock divider value and PCLK is
the peripheral clock.
Table 751. Register overview: C_CAN0 (base address 0x400E 2000)
Name
CNTL
STAT
EC
BT
INT
TEST
BRPE
-
IF1_CMDREQ
IF1_CMDMSK_W
IF1_CMDMSK_R
IF1_MSK1
IF1_MSK2
IF1_ARB1
IF1_ARB2
IF1_MCTRL
IF1_DA1
IF1_DA2
IF1_DB1
IF1_DB2
All information provided in this document is subject to legal disclaimers.
RO
Access
RO
-
Rev. 00.13 — 20 July 2011
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
Description
CAN control
Status register
Error counter
Bit timing register
Interrupt register
Test register
Baud rate prescaler extension register
Reserved
Message interface 1 command request 0x0001
Message interface 1 command mask
(write direction)
Message interface 1 command mask
(read direction)
Message interface 1 mask 1
Message interface 1 mask 2
Message interface 1 arbitration 1
Message interface 1 arbitration 2
Message interface 1 message control
Message interface 1 data A1
Message interface 1 data A2
Message interface 1 data B1
Message interface 1 data B2
Chapter 36: LPC18xx C_CAN
Table
UM10430
© NXP B.V. 2011. All rights reserved.
751. Additionally,
Reset
value
0x0001
0x0000
0x0000
0x2301
0x0000
-
0x0000
-
0x0000
0x0000
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
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