LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 525

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.2.6 Receive descriptor acquisition
22.8.2.7 Receive frame processing
If software has enabled time stamping through CSR, when a valid time stamp value is not
available for the frame (for example, because the receive FIFO was full before the time
stamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise
(that is, if time stamping is not enabled), the RDES2 and RDES3 remain unchanged.
The Receive Engine always attempts to acquire an extra descriptor in anticipation of an
incoming frame. Descriptor acquisition is attempted if any of the following conditions is
satisfied:
The MAC transfers the received frames to the Host memory only when the frame passes
the address filter and frame size is greater than or equal to configurable threshold bytes
set for the Receive FIFO of MTL, or when the complete frame is written to the FIFO in
Store-and-Forward mode.
If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive
All bit 3 is set in the MAC Frame Filter register;
64 bytes, because of collision or premature termination, can be purged from the MTL
Receive FIFO.
After 64 (configurable threshold) bytes have been received, the MTL block requests the
DMA block to begin transferring the frame data to the Receive Buffer pointed to by the
current descriptor. The DMA sets First Descriptor (RDES0[9]) after the DMA Host
Interface (AHB or MDC) becomes ready to receive a data transfer (if DMA is not fetching
transmit data from the host), to delimit the frame. The descriptors are released when the
Own (RDES[31]) bit is reset to 0, either as the Data buffer fills up or as the last segment of
the frame is transferred to the Receive buffer. If the frame is contained in a single
descriptor, both Last Descriptor (RDES[8]) and First Descriptor (RDES[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES[8]) bit, and releases
the RDES0 status bits in the previous frame descriptor. Then the DMA sets Receive
Interrupt (Register 5[6]). The same process repeats unless the DMA encounters a
descriptor flagged as being owned by the host. If this occurs, the Receive Process sets
Receive Buffer Unavailable (DMA Status register
state. The position in the receive list is retained.
•
•
•
•
•
The receive Start/Stop bit (DMA Operation Mode register
immediately after being placed in the Run state.
The data buffer of current descriptor is full before the frame ends for the current
transfer.
The controller has completed frame reception, but the current Receive Descriptor is
not yet closed.
The receive process has been suspended because of a host-owned buffer
(RDES0[31] = 0) and a new frame is received.
A Receive poll demand has been issued.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table
Table
404). Frames that are shorter than
427) and then enters the Suspend
Chapter 22: LPC18xx Ethernet
Table
428) has been set
UM10430
© NXP B.V. 2011. All rights reserved.
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