LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 806

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

36.1 How to read this chapter
36.2 Basic configuration
36.3 Features
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User manual
The C_CAN0/1 controllers are available on all LPC18xx parts.
The C_CAN is configured as follows:
Table 749. C_CAN clocking and power control
Clock to the C_CAN0 register interface
and C_CAN0 peripheral clock.
Clock to the C_CAN1 register interface
and C_CAN1 peripheral clock.
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UM10430
Chapter 36: LPC18xx C_CAN
Rev. 00.13 — 20 July 2011
See
The C_CAN0 is reset by the CAN0_RST (reset # 55).
The C_CAN1 is reset by the CAN1_RST (reset # 56).
The ORed C_CAN0 and C_CAN1 interrupt is connected to slot # 12 in the Event
router.
The C_CAN0 interrupt is connected to interrupt #51 in the NVIC.
The C_CAN1 interrupt is connected to interrupt #43 in the NVIC.
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
Table 749
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_APB3_CLK
BASE_APB1_CLK
Branch clock
CLK_APB3_CAN0
CLK_APB1_CAN1
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
150 MHz
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